Re: [PATCH net-next 3/3] net: phy: motorcomm: Enable analog frontend on YT8531S

[Yao Zi]

On Tue, Sep 01, 2026 at 04:21:36PM +0200, Maxime Chevallier wrote:
> 
> 
> On 9/1/26 15:59, Paolo Abeni wrote:
> > On 8/31/26 9:37 AM, Maxime Chevallier wrote:
> >> The YT6801 PCIe NIC includes the dwmac-motorcomm IP for the MAC part, as
> >> well as a YT8531S PHY, configured in GMII mode.
> >>
> >> It seems this PHY requires the Analog Front-end (AFE) DAC clock to be
> >> enabled for link to reliably establish, otherwise the link just doesn't
> >> come up.
> >>
> >> Let's enable it at config_init().
> >>
> >> This logic has been extracted from the vendor driver provided by
> >> Motorcomm.
> >>
> >> It's really unclear if this is specific to the integrated version of
> >> that PHY, and how this potentially interacts with the fiber mode this
> >> PHY supports, so this configuration is only enabled when the interface
> >> is GMII, i.e. the PHY is integrated.
> >>
> >> With this, the PHY reliably establishes link and the YT6801 PCIe card
> >> becomes fully functional.
> >>
> >> Signed-off-by: Maxime Chevallier <maxime.chevallier@xxxxxxxxxxx>
> >> ---
> >>  drivers/net/phy/motorcomm.c | 14 +++++++++++++-
> >>  1 file changed, 13 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c
> >> index 36c229460a77..90a4f86f2758 100644
> >> --- a/drivers/net/phy/motorcomm.c
> >> +++ b/drivers/net/phy/motorcomm.c
> >> @@ -144,6 +144,11 @@
> >>  #define YT8521_CLOCK_GATING_REG			0xC
> >>  #define YT8521_CGR_RX_CLK_EN			BIT(12)
> >>  
> >> +/* Analog front-end control register 3 */
> >> +#define YT8531S_EXT_AFE_CTRL3			0x12
> >> +/* Analog front-end DAC clock enable */
> >> +#define YT8531S_AFE_CTRL3_CLKDAC_AON		BIT(13)
> >> +
> >>  #define YT8521_EXTREG_SLEEP_CONTROL1_REG	0x27
> >>  #define YT8521_ESC1R_SLEEP_SW			BIT(15)
> >>  #define YT8521_ESC1R_PLLON_SLP			BIT(14)
> >> @@ -1740,8 +1745,15 @@ static int yt8531s_config_init(struct phy_device *phydev)
> >>  	if (ret)
> >>  		goto err_restore_page;
> >>  
> >> -	if (phy_interface_is_rgmii(phydev))
> >> +	if (phy_interface_is_rgmii(phydev)) {
> >>  		ret = yt8531_set_ds(phydev);
> >> +		if (ret)
> >> +			goto err_restore_page;
> >> +	}
> >> +
> >> +	if (phydev->interface == PHY_INTERFACE_MODE_GMII)
> >> +		ret = ytphy_modify_ext(phydev, YT8531S_EXT_AFE_CTRL3,
> >> +				       0, YT8531S_AFE_CTRL3_CLKDAC_AON);
> > 
> > Sashiko suspects this will not survive a suspend/resume:
> > 
> > https://netdev-ai.bots.linux.dev/sashiko/#/patchset/20260831073747.361482-1-maxime.chevallier%40bootlin.com
> 
> hmm sashiko may be right, worth adding right now as it seems there are
> some discussions already on motorcomm suspend/resume issues, let me spin
> a V2
> 
> Thanks !

Yes, suspend/resume already works for some time on devices unaffected
by the issue under discussion. It looks good to me apart from this.
I'll call some guys to test for regressions on devices proven to work
before.

> Maxime
> 

Best regards,
Yao Zi