Re: [PATCH v5 3/4] power: sequencing: Add Renesas RZ/G3L Power Ready driver

[Bartosz Golaszewski]

On Wed, 26 Aug 2026 14:27:25 +0200, Biju <biju.das.au@xxxxxxxxx> said:
> From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
>
> Add a power sequencing driver for the Renesas RZ/G3L PWRRDY module,
> which signals power readiness for various IPs (USB, DSI, CSI etc.) on the
> SoC. The driver binds as an auxiliary device to the parent SYSC driver,
> using its regmap to toggle the SYS_PWRRDY_N register bits, and exposes
> {usb,dsi,csi}-pwrrdy pwrseq targets.
>
> Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> ---

I would prefer to see a stricter .match() but since the parent is the soc node
we may get away without it.

What is the merge strategy here? Are patches 2 and 3 independent from 1 and 4
at build time?

Bart