Re: [PATCH v8 1/9] dt-bindings: display: renesas,rzg2l-du: Document RZ/G3E SoC

From: Krzysztof Kozlowski

Date: Wed Sep 02 2026 - 02:40:51 EST


On Fri, Aug 28, 2026 at 02:21:04PM +0200, Tommaso Merciai wrote:
> The RZ/G3E Soc has 2 LCD controller (LCDC), contain a Frame Compression
> Processor (FCPVD), a Video Signal Processor (VSPD), Video Signal
> Processor (VSPD), and Display Unit (DU).
>
> - LCDC0 supports DSI and LVDS (single or dual-channel) outputs.
> - LCDC1 supports DSI, LVDS (single-channel), and RGB outputs.
>
> Add new SoC-specific compatible string 'renesas,r9a09g047-du'.
>
> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@xxxxxxxxxxxxxx>
> ---
> v7->v8:
> - Rebased on top of RZ/G3L du support [1]
> - Modelled using ports/port instead of port/ep.
> [1] https://lore.kernel.org/all/20260826174854.199139-1-biju.das.jz@xxxxxxxxxxxxxx/
> - Improved commit msg and commit body.
>
> v6->v7:
> - Rebased on top of [1]
> [1] https://lore.kernel.org/all/20260429170012.366537-1-prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx/
> - Use single DRM device aggregating both DU instances (1 DU dt node),
> modelling single port for each DU0, DU1 and multiple endpoints for
> outputs.
>
> v5->v6:
> - Extend patternProperties from "^port@[0-1]$" to "^port@[0-3]$" and
> explicitly disable port@2 and port@3 for existing SoCs that do not expose
> them.
> - Reworked ports numbering + improved/fixed ports descriptions in the
> bindings documentation.
> - Improved commit body.
>
> v4->v5:
> - Dropped renesas,id property and updated bindings
> accordingly.
>
> v2->v3:
> - No changes.
>
> v2->v3:
> - No changes.
>
> v1->v2:
> - Use single compatible string instead of multiple compatible strings
> for the two DU instances, leveraging a 'renesas,id' property to
> differentiate between DU0 and DU1.
> - Updated commit message accordingly.
>
> .../bindings/display/renesas,rzg2l-du.yaml | 95 ++++++++++++++++++-
> 1 file changed, 91 insertions(+), 4 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
> index 5c9b15a09dee..d44c7c0add8d 100644
> --- a/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
> +++ b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
> @@ -21,6 +21,7 @@ properties:
> - renesas,r9a07g043u-du # RZ/G2UL
> - renesas,r9a07g044-du # RZ/G2{L,LC}
> - renesas,r9a08g046-du # RZ/G3L
> + - renesas,r9a09g047-du # RZ/G3E
> - renesas,r9a09g057-du # RZ/V2H(P)
> - renesas,r9a09g077-du # RZ/T2H
> - items:
> @@ -35,25 +36,51 @@ properties:
> - const: renesas,r9a09g077-du # RZ/T2H fallback
>
> reg:
> - maxItems: 1
> + minItems: 1
> + maxItems: 2
> +
> + reg-names:
> + items:
> + - const: du.0
> + - const: du.1

du is the name of the device, thus calling items "0" and "1" is pretty
pointless - indices already define that. Please drop the reg-names.

>
> interrupts:
> - maxItems: 1
> + minItems: 1
> + maxItems: 2
> +
> + interrupt-names:
> + items:
> + - const: du.0
> + - const: du.1

Same here

>
> clocks:
> + minItems: 3
> items:
> - description: Main clock
> - description: Register access clock
> - description: Video clock
> + - description: Main clock for DU1
> + - description: Register access clock for DU1
> + - description: Video clock for DU1
>
> clock-names:
> + minItems: 3
> items:
> - const: aclk
> - const: pclk
> - const: vclk
> + - const: aclk1
> + - const: pclk1
> + - const: vclk1
>
> resets:
> - maxItems: 1
> + minItems: 1
> + maxItems: 2
> +
> + reset-names:
> + items:
> + - const: resetn
> + - const: resetn1

Drop reset-names

>
> power-domains:
> maxItems: 1
> @@ -66,7 +93,7 @@ properties:
> model-dependent. Each port shall have a single endpoint.
>
> patternProperties:
> - "^port@[0-2]$":
> + "^port@[0-3]$":
> $ref: /schemas/graph.yaml#/properties/port
> unevaluatedProperties: false
>
> @@ -110,6 +137,7 @@ allOf:
> description: DPI
> port@1: false
> port@2: false
> + port@3: false

Best regards,
Krzysztof