Re: [PATCH v5 3/4] power: sequencing: Add Renesas RZ/G3L Power Ready driver

[Bartosz Golaszewski]

On Wed, 2 Sep 2026 09:10:45 +0200, Geert Uytterhoeven
<geert@xxxxxxxxxxxxxx> said:
> Hi Bartosz,
>
> On Tue, 1 Sept 2026 at 18:15, Bartosz Golaszewski <brgl@xxxxxxxxxx> wrote:
>> On Wed, 26 Aug 2026 14:27:25 +0200, Biju <biju.das.au@xxxxxxxxx> said:
>> > From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
>> >
>> > Add a power sequencing driver for the Renesas RZ/G3L PWRRDY module,
>> > which signals power readiness for various IPs (USB, DSI, CSI etc.) on the
>> > SoC. The driver binds as an auxiliary device to the parent SYSC driver,
>> > using its regmap to toggle the SYS_PWRRDY_N register bits, and exposes
>> > {usb,dsi,csi}-pwrrdy pwrseq targets.
>> >
>> > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
>
>> What is the merge strategy here? Are patches 2 and 3 independent from 1 and 4
>> at build time?
>
> I think so: one can safely select a non-existing symbol in Kconfig.
>
> So once you're happy with this patch, I can take patches 1 and 4
> through renesas-devel.
>

I picked up 2 and 3.

Bart