Re: [RESEND Patch v10 00/23] Support SIMD/eGPRs/SSP registers sampling for perf

[Mi, Dapeng]

On 9/2/2026 7:56 PM, Peter Zijlstra wrote:
> On Tue, Sep 01, 2026 at 04:55:27PM +0800, Mi, Dapeng wrote:
>> Hi Peter,
>>
>> Kindly ping ... Not sure if you have bandwidth to review this patch series? 
>>
>> Currently all review comments are addressed and finally Sashiko can't find
>> issues. :)
> Ok, so I started going through things and the only bit I've found so far
> is that I'm not sure about the below bits.
>
> Is that really something we want to expose as UAPI? It seems to me
> userspace that is interested in SIMD stuff knows this stuff already.

Thanks for reviewing. :)

I ever tried to remove these macros from this UAPI header, but it seems
this is still the best place as below two reasons.

1. These SIMD register number and qword length are shared by both kernel
and user space. If they are not exposed to user space, user space still
needs to define them.

2. In kernel, these macros are used by the files
arch/x86/kernel/perf_regs.c and arch/x86/events/perf_event.h, it seems
arch/x86/include/uapi/asm/perf_regs.h is the best place to define these
macros just like the normal GPR macros.


>
> Anyway, let me continue looking.
>
>
> ---
> diff --git a/arch/x86/include/uapi/asm/perf_regs.h b/arch/x86/include/uapi/asm/perf_regs.h
> index 7c9d2bb3833b..faaa82df688d 100644
> --- a/arch/x86/include/uapi/asm/perf_regs.h
> +++ b/arch/x86/include/uapi/asm/perf_regs.h
> @@ -2,6 +2,8 @@
>  #ifndef _ASM_X86_PERF_REGS_H
>  #define _ASM_X86_PERF_REGS_H
>  
> +#include <linux/bits.h>
> +
>  enum perf_event_x86_regs {
>  	PERF_REG_X86_AX,
>  	PERF_REG_X86_BX,
> @@ -54,5 +82,30 @@ enum perf_event_x86_regs {
>  };
>  
>  #define PERF_REG_EXTENDED_MASK	(~((1ULL << PERF_REG_X86_XMM0) - 1))
> +#define PERF_X86_EGPRS_MASK	__GENMASK_ULL(PERF_REG_X86_R31, PERF_REG_X86_R16)
> +
> +enum {
> +	PERF_X86_SIMD_XMM_REGS      = 16,
> +	PERF_X86_SIMD_YMM_REGS      = 16,
> +	PERF_X86_SIMD_ZMM_REGS      = 32,
> +	PERF_X86_SIMD_VEC_REGS_MAX  = PERF_X86_SIMD_ZMM_REGS,
> +
> +	PERF_X86_SIMD_OPMASK_REGS   = 8,
> +	PERF_X86_SIMD_PRED_REGS_MAX = PERF_X86_SIMD_OPMASK_REGS,
> +};
> +
> +#define PERF_X86_SIMD_PRED_MASK	__GENMASK(PERF_X86_SIMD_PRED_REGS_MAX - 1, 0)
> +#define PERF_X86_SIMD_VEC_MASK	__GENMASK_ULL(PERF_X86_SIMD_VEC_REGS_MAX - 1, 0)
> +
> +#define PERF_X86_H16ZMM_BASE		16
> +
> +enum {
> +	/* 1 qword = 8 bytes */
> +	PERF_X86_OPMASK_QWORDS   = 1,
> +	PERF_X86_XMM_QWORDS      = 2,
> +	PERF_X86_YMM_QWORDS      = 4,
> +	PERF_X86_ZMM_QWORDS      = 8,
> +	PERF_X86_SIMD_QWORDS_MAX = PERF_X86_ZMM_QWORDS,
> +};
>  
>  #endif /* _ASM_X86_PERF_REGS_H */