Re: [PATCH v2 2/2] x86/mce: Avoid arming periodic polling timer when not required

[Aaron Tomlin]

On Tue, Sep 01, 2026 at 10:02:13PM -0400, Aaron Tomlin wrote:
> On x86 platforms, the Machine Check Architecture (MCA) subsystem arms a
> per-CPU, pinned standard timer (mce_timer) to periodically poll hardware
> banks for "silent" corrected machine check errors. Because mce_timer is
> pinned to the local CPU via TIMER_PINNED, the timer core cannot migrate
> its expiration to a housekeeping CPU, causing periodic latency jitter on
> isolated cores.
> 
> On Intel systems supporting Corrected Machine Check Interrupt (CMCI),
> hardware generates an interrupt for banks with CMCI enabled, clearing
> their respective bits in mce_poll_banks. However, for banks where
> MCI_CTL2_CMCI_EN does not stick (such as the Power Control Unit bank),
> Linux historically assumed software polling was required and left the
> bank flagged in mce_poll_banks.
> 
> Per the Intel SDM (Vol 3B, Section 18.5 "Corrected Machine Check Error
> Interrupt"), if bit 30 of IA32_MCi_CTL2 is zero, no CMCI is available
> for that bank and no corrected or Uncorrected No Action Required (UCNA)
> errors will be reported on that bank. Therefore, polling such banks is
> redundant and wasteful.
> 
> Clear non-CMCI banks from mce_poll_banks in cmci_claim_bank() on
> CMCI-capable CPUs, and amend should_enable_timer() to:
>     1.  Check bitmap_empty(mce_poll_banks) so that mce_timer is never
>         armed when no banks on that CPU require software polling.
> 
>     2.  Pin the MCE polling timer to a HK_TYPE_TIMER housekeeping CPU,
>         sparing isolated nohz_full cores from periodic wakeups on
>         systems requiring mce_poll_banks polling.
> 
> On modern CMCI-supported platforms, mce_timer is eliminated system-wide
> in steady state. On legacy or polling-only configurations, housekeeping
> CPUs perform routine polling whilst isolated CPUs remain jitter-free.
> Polling fallback during active error storms is fully preserved.
> 
> Suggested-by: Tony Luck <tony.luck@xxxxxxxxx>
> Signed-off-by: Aaron Tomlin <atomlin@xxxxxxxxxxx>
> ---
>  arch/x86/kernel/cpu/mce/core.c  |  7 +++++++
>  arch/x86/kernel/cpu/mce/intel.c | 11 ++++++-----
>  2 files changed, 13 insertions(+), 5 deletions(-)

Hi Tony,

As per Sashiko [1], the last paragraph should be updated to avoid
confusion, thank you:

    "On systems requiring software polling such legacy platforms lacking
     CMCI or when booted with mce=no_cmci, the mce_timer is restricted to
     housekeeping CPUs. While this intentionally leaves core-private banks
     (e.g., L1/L2 caches) on isolated cores exempt from periodic polling to
     guarantee zero timer jitter, housekeeping CPUs continue to harvest
     telemetry from their own banks as well as shared package-level
     resources. Synchronous (#MC) exceptions on isolated cores remain
     entirely unaffected."


[1]: https://sashiko.dev/#/patchset/20260902020234.149814-1-atomlin%40atomlin.com

Kind regards,
-- 
Aaron Tomlin