Re: [PATCH] PCI: tegra264: Fix Link Capabilities register offset

[Manivannan Sadhasivam]

On Thu, 27 Aug 2026 17:39:19 +0800, Linmao Li wrote:
> The PCI Express Link Capabilities and Link Status registers are at offsets
> 0x0c and 0x12 from the capability header, respectively.  Since the driver
> uses 0x5a for Link Status, Link Capabilities starts at 0x54, not 0x56.
> 
> Reading a 16-bit value at 0x56 returns the upper half of the Link
> Capabilities register.  When a hotplug-capable port has no link during
> probe, tegra264_pcie_icc_set() consequently derives the maximum speed and
> width from unrelated bits and requests the wrong interconnect bandwidth.
> 
> [...]

Applied, thanks!

[1/1] PCI: tegra264: Fix Link Capabilities register offset
      commit: ed17593383fe3926950cae250842783630f32697

Best regards,
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