Re: [PATCH RESEND] xor: add missing vzeroupper to AVX code

[Eric Biggers]

On Wed, Sep 02, 2026 at 03:37:06PM +0200, Christoph Hellwig wrote:
> On Mon, Aug 31, 2026 at 02:22:48PM -0700, Eric Biggers wrote:
> > Since the AVX optimized XOR code uses YMM registers, execute vzeroupper
> > before returning from it.  This is needed to avoid degrading the
> > performance of any later SSE code that may happen to be executed.
> > 
> > Fixes: ea4d26ae24e5 ("raid5: add AVX optimized RAID5 checksumming")
> > Cc: stable@xxxxxxxxxxxxxxx
> > Signed-off-by: Eric Biggers <ebiggers@xxxxxxxxxx>
> > ---
> > 
> > This didn't get taken through the x86 tree.  Andrew, it seems you're
> > taking patches to lib/raid/.  Can you apply this one?
> 
> Can we do kernel_avx_{begin,end} instead of having to open code
> and document this everywhere, please?

Again, there are cases in the kernel where both AVX and SSE are used
within a single kernel-mode FPU section, or where a CPU feature check
occurs within the section and one or the other is used.  So that
abstraction will not work as-is, and it would be different from all
userspace code as well.  If you'd like to try to refactor everything you
can try to do so, but let's not block fixing these bugs first.

Also, AVX != "vzeroupper is needed".  The relevant thing is the width of
the registers used.  There is 128-bit AVX code.

- Eric