Re: [PATCH RESEND] xor: add missing vzeroupper to AVX code

[Eric Biggers]

On Wed, Sep 02, 2026 at 07:19:56PM +0100, David Laight wrote:
> It also depends on the instruction encoding used for 128-bit AVX code.
> If the VEX encoding is used the high bits of the ymm registers get cleared
> (rather than preserved) and you get different delays.
> Flipping to/from VEX encoded 128bit instructions adds delays on some cpu.

All instructions operating on XMM registers that aren't VEX or EVEX
coded are typically called "SSE instructions", not AVX.  (Even if they
require something that wasn't in the original SSE.)

The point is that "128-bit AVX" exists, typically because the AES and
carryless multiplication instructions have typically been 128-bit only.
256 and 512-bit support for those came much later than the rest of AVX.

Just to give a random example, aes_xts_encrypt_aesni_avx() and
aes_xts_decrypt_aesni_avx() are "128-bit AVX".  And they indeed don't do
vzeroupper, because they don't need to.

Some cases such as lib/crc/x86/crc-pclmul-template.S skip providing
128-bit AVX code and just have the CPUs that could run it instead run
the 128-bit SSE code, but that is a tradeoff made in those cases.

- Eric