Re: [PATCH v1 2/8] x86/sev: Add support for Alternate Injection

[Borislav Petkov]

On Sat, Aug 29, 2026 at 03:39:40AM +0000, Melody Wang wrote:
> The Alternate Injection feature is a method to protect an AMD
> confidential computing guest from malicious injection attacks. It allows

" ... a SNP guest... " - simpler.

> the guest to control the interrupt injection.
> 
> When this feature is enabled, interrupts are injected with the help of
> an agent called a Secure VM Service Module (SVSM) which executes in the
> security realm of the guest and uses Restricted Injection as the sole
> method to receive interrupts from the hypervisor.
> 
> Add support for Alternate Injection enablement.

s/ enablement//

> Signed-off-by: Melody Wang <huibo.wang@xxxxxxx>
> ---
>  arch/x86/Kconfig                   | 14 ++++++++++++++
>  arch/x86/boot/compressed/sev.c     |  2 +-
>  arch/x86/coco/core.c               |  3 +++
>  arch/x86/coco/sev/core.c           |  2 +-
>  arch/x86/include/asm/cpufeatures.h |  1 +
>  arch/x86/include/asm/msr-index.h   |  4 ++--
>  include/linux/cc_platform.h        |  8 ++++++++
>  7 files changed, 30 insertions(+), 4 deletions(-)

...

> diff --git a/arch/x86/coco/core.c b/arch/x86/coco/core.c
> index 989ca9f72ba3..aabda3ddc0e2 100644
> --- a/arch/x86/coco/core.c
> +++ b/arch/x86/coco/core.c
> @@ -107,6 +107,9 @@ static bool noinstr amd_cc_platform_has(enum cc_attr attr)
>  	case CC_ATTR_SNP_SECURE_AVIC:
>  		return sev_status & MSR_AMD64_SNP_SECURE_AVIC;
>  
> +	case CC_ATTR_SNP_ALTERNATE_INJECTION:
> +		return sev_status & MSR_AMD64_SNP_ALTERNATE_INJ;

Sashiko is complaining here:

| Does this attribute evaluate the host status or the guest status?
| 
| The implementation in amd_cc_platform_has() checks sev_status, which 
| represents the SEV capability of the executing guest. However, the doc comment
| for CC_ATTR_SNP_ALTERNATE_INJECTION below states it checks if "The host kernel
| is running with the necessary features". Could the documentation be updated to
| match the actual implementation?

Because of the comment over CC_ATTR_SNP_ALTERNATE_INJECTION talking about the
host running with the necessary features, blabla. Yeah, sev_status dumps guest
bits and the alternate injection bit is set in the VMSA by the SVSM and so
yeah, maybe we should tone down the "host" speech in the comment...

> diff --git a/arch/x86/coco/sev/core.c b/arch/x86/coco/sev/core.c
> index cc292d7c6fd1..c54269366278 100644
> --- a/arch/x86/coco/sev/core.c
> +++ b/arch/x86/coco/sev/core.c
> @@ -78,7 +78,7 @@ static const char * const sev_status_feat_names[] = {
>  	[MSR_AMD64_SNP_VTOM_BIT]		= "vTom",
>  	[MSR_AMD64_SNP_REFLECT_VC_BIT]		= "ReflectVC",
>  	[MSR_AMD64_SNP_RESTRICTED_INJ_BIT]	= "RI",
> -	[MSR_AMD64_SNP_ALT_INJ_BIT]		= "AI",
> +	[MSR_AMD64_SNP_ALTERNATE_INJ_BIT]	= "AI",
>  	[MSR_AMD64_SNP_DEBUG_SWAP_BIT]		= "DebugSwap",
>  	[MSR_AMD64_SNP_PREVENT_HOST_IBS_BIT]	= "NoHostIBS",
>  	[MSR_AMD64_SNP_BTB_ISOLATION_BIT]	= "BTBIsol",
> diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
> index f70ee74b5f92..a53e40a3982c 100644
> --- a/arch/x86/include/asm/cpufeatures.h
> +++ b/arch/x86/include/asm/cpufeatures.h
> @@ -466,6 +466,7 @@
>  #define X86_FEATURE_SNP_SECURE_TSC	(19*32+ 8) /* SEV-SNP Secure TSC */
>  #define X86_FEATURE_V_TSC_AUX		(19*32+ 9) /* Virtual TSC_AUX */
>  #define X86_FEATURE_SME_COHERENT	(19*32+10) /* hardware-enforced cache coherency */
> +#define X86_FEATURE_ALTERNATE_INJECTION	(19*32+13) /* SEV Alternate Injection */

Sashiko: Does this new feature addition need to be synchronized with the
kernel tools directory?

Answer: no. We sync those only when needed.

Also, make the comment /* SEV-SNP Alternate ... */

as it is a SNP feature.

>  #define X86_FEATURE_DEBUG_SWAP		(19*32+14) /* "debug_swap" SEV-ES full debug state swap support */
>  #define X86_FEATURE_RMPREAD		(19*32+21) /* RMPREAD instruction */
>  #define X86_FEATURE_SEGMENTED_RMP	(19*32+23) /* Segmented RMP support */
> diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
> index 3a8e51a0c9e8..473a3ba86a2d 100644
> --- a/arch/x86/include/asm/msr-index.h
> +++ b/arch/x86/include/asm/msr-index.h
> @@ -721,8 +721,8 @@
>  #define MSR_AMD64_SNP_REFLECT_VC	BIT_ULL(MSR_AMD64_SNP_REFLECT_VC_BIT)
>  #define MSR_AMD64_SNP_RESTRICTED_INJ_BIT 5
>  #define MSR_AMD64_SNP_RESTRICTED_INJ	BIT_ULL(MSR_AMD64_SNP_RESTRICTED_INJ_BIT)
> -#define MSR_AMD64_SNP_ALT_INJ_BIT	6
> -#define MSR_AMD64_SNP_ALT_INJ		BIT_ULL(MSR_AMD64_SNP_ALT_INJ_BIT)
> +#define MSR_AMD64_SNP_ALTERNATE_INJ_BIT	6
> +#define MSR_AMD64_SNP_ALTERNATE_INJ	BIT_ULL(MSR_AMD64_SNP_ALTERNATE_INJ_BIT)
>  #define MSR_AMD64_SNP_DEBUG_SWAP_BIT	7
>  #define MSR_AMD64_SNP_DEBUG_SWAP	BIT_ULL(MSR_AMD64_SNP_DEBUG_SWAP_BIT)
>  #define MSR_AMD64_SNP_PREVENT_HOST_IBS_BIT 8

Sashiko: Is it necessary to update tools/arch/x86/include/asm/msr-index.h with this
macro rename as well?

Yeah, we probably should for completeness' sake.

-- 
Regards/Gruss,
    Boris.

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