[PATCH v5 1/2] clk: rs9: Add clock index range check to rs9_of_clk_get()
From: Geert Uytterhoeven
Date: Thu Sep 03 2026 - 06:13:48 EST
rs9_of_clk_get() does not validate the clock index in the passed
DT clock specifier. If DT specifies an incorrect and out-of-range
index, this will access memory beyond the end of the clk_dif[] array.
Fix by this adding a range check to rs9_of_clk_get().
Fixes: 892e0ddea1aa6f70 ("clk: rs9: Add Renesas 9-series PCIe clock generator driver")
Signed-off-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
Reviewed-by: Marek Vasut <marek.vasut+renesas@xxxxxxxxxxx>
---
v5:
- Add Reviewed-by,
v4:
- Put in a series,
v3:
- Add error message,
v2:
- Just add the missing range check; the conversion to
of_clk_hw_onecell_get() can be done later.
v1: "[PATCH] clk: rs9: Convert to clk_hw_onecell_data and
of_clk_hw_onecell_get()"
https://lore.kernel.org/a6dce17b15d29a257d09fe0edc199a14c297f1a8.1768836042.git.geert+renesas@xxxxxxxxx
---
drivers/clk/clk-renesas-pcie.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/clk/clk-renesas-pcie.c b/drivers/clk/clk-renesas-pcie.c
index 564550c803896756..f3376c29007aa92d 100644
--- a/drivers/clk/clk-renesas-pcie.c
+++ b/drivers/clk/clk-renesas-pcie.c
@@ -276,6 +276,11 @@ rs9_of_clk_get(struct of_phandle_args *clkspec, void *data)
struct rs9_driver_data *rs9 = data;
unsigned int idx = clkspec->args[0];
+ if (idx >= rs9->chip_info->num_clks) {
+ pr_err("%s: Invalid clock index %u\n", __func__, idx);
+ return ERR_PTR(-EINVAL);
+ }
+
return rs9->clk_dif[idx];
}
--
2.43.0