RE: [PATCH v4 14/27] vfio: Add CXL region type for the HDM region
From: Manish Honap
Date: Thu Sep 03 2026 - 06:30:59 EST
> -----Original Message-----
> From: Alex Williamson <alex@xxxxxxxxxxx>
> Sent: Friday, August 28, 2026 4:14 AM
> To: Manish Honap <mhonap@xxxxxxxxxx>
> Cc: jgg@xxxxxxxx; Ankit Agrawal <ankita@xxxxxxxxxx>; jic23@xxxxxxxxxx;
> dave.jiang@xxxxxxxxx; alejandro.lucero-palau@xxxxxxx; Srirangan Madhavan
> <smadhavan@xxxxxxxxxx>; corbet@xxxxxxx; skhan@xxxxxxxxxxxxxxxxxxx;
> dave@xxxxxxxxxxxx; alison.schofield@xxxxxxxxx; vishal.l.verma@xxxxxxxxx;
> iweiny@xxxxxxxxxx; ming.li@xxxxxxxxxxxx; Yishai Hadas
> <yishaih@xxxxxxxxxx>; Shameer Kolothum Thodi
> <skolothumtho@xxxxxxxxxx>; kevin.tian@xxxxxxxxx; bhelgaas@xxxxxxxxxx;
> dmatlack@xxxxxxxxxx; kees@xxxxxxxxxx; gustavoars@xxxxxxxxxx; Neo Jia
> <cjia@xxxxxxxxxx>; Krishnakant Jaju <kjaju@xxxxxxxxxx>; Vikram Sethi
> <vsethi@xxxxxxxxxx>; Zhi Wang <zhiw@xxxxxxxxxx>; linux-
> doc@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx; kvm@xxxxxxxxxxxxxxx;
> linux-cxl@xxxxxxxxxxxxxxx; linux-pci@xxxxxxxxxxxxxxx; linux-
> kselftest@xxxxxxxxxxxxxxx; linux-hardening@xxxxxxxxxxxxxxx; alex@xxxxxxxxxxx
> Subject: Re: [PATCH v4 14/27] vfio: Add CXL region type for the HDM region
>
> External email: Use caution opening links or attachments
>
>
> On Thu, 13 Aug 2026 15:06:18 +0530
> <mhonap@xxxxxxxxxx> wrote:
>
> > From: Manish Honap <mhonap@xxxxxxxxxx>
> >
> > A CXL Type-2 device exposes its HDM memory to the guest as a dedicated
> > VFIO region rather than a PCI BAR. Add a CXL region type and a memory
> > sub-type for it; vfio-cxl registers the window under these so
> > userspace can discover and map it.
> >
> > Signed-off-by: Manish Honap <mhonap@xxxxxxxxxx>
> > ---
> > include/uapi/linux/vfio.h | 5 +++++
> > 1 file changed, 5 insertions(+)
> >
> > diff --git a/include/uapi/linux/vfio.h b/include/uapi/linux/vfio.h
> > index 5de618a3a5ee..540e62312671 100644
> > --- a/include/uapi/linux/vfio.h
> > +++ b/include/uapi/linux/vfio.h
> > @@ -345,6 +345,7 @@ struct vfio_region_info_cap_type {
> > #define VFIO_REGION_TYPE_GFX (1)
> > #define VFIO_REGION_TYPE_CCW (2)
> > #define VFIO_REGION_TYPE_MIGRATION_DEPRECATED (3)
> > +#define VFIO_REGION_TYPE_CXL (4)
> >
> > /* sub-types for VFIO_REGION_TYPE_PCI_* */
> >
> > @@ -373,6 +374,10 @@ struct vfio_region_info_cap_type {
> > /* sub-types for VFIO_REGION_TYPE_GFX */
> > #define VFIO_REGION_SUBTYPE_GFX_EDID (1)
> >
> > +/* sub-types for VFIO_REGION_TYPE_CXL */
> > +/* CXL.mem HDM region of a Type-2 device, mmap-able */
> > +#define VFIO_REGION_SUBTYPE_CXL_MEM (1)
> > +
> > /**
> > * struct vfio_region_gfx_edid - EDID region layout.
> > *
>
> CXL has a PCI vendor ID, it's even used in the dvsec capability. Why not use a
> PCI vendor type region? Thanks,
>
> Alex
Yes, I will switch to a PCI vendor-type region with the CXL vendor ID instead of CXL
region type.
Manish