Re: [PATCH v3 07/12] clk: qcom: ipq-cmn-pll: Add PON reference clock support

[Konrad Dybcio]

On 8/14/26 2:48 PM, Luo Jie wrote:
> The PON (Passive Optical Network) reference clock's parent is
> cmn_pll_div2 (CMN PLL rate / 2); it is then further divided by a
> configurable 8-bit divider (1-255). The clock supports two modes:

[...]

> +static const struct clk_ops clk_pon_clk_ops = {
> +	.enable = clk_pon_clk_enable,

clk_enable_regmap
> +	.disable = clk_pon_clk_disable,

clk_disable_regmap

> +	.is_enabled = clk_pon_clk_is_enabled,

clk_is_enabled_regmap

> +	.recalc_rate = clk_pon_clk_recalc_rate,
> +	.determine_rate = clk_pon_clk_determine_rate,
> +	.set_rate = clk_pon_clk_set_rate,

These seem genuinely new

Konrad