Re: [PATCH 2/4] clk: renesas: r9a08g046: Add PCIe clocks and reset

[Geert Uytterhoeven]

On Tue, 25 Aug 2026 at 11:50, Biju <biju.das.au@xxxxxxxxx> wrote:
> From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
>
> Add the PCIe module clocks (ACLK, CLKL1PM, CLK_PMU) and the PCIe
> reset signal for the RZ/G3L (R9A08G046) SoC, along with the P8
> fixed clock required as the parent for CLKL1PM.
>
> Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>

Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
i.e. will queue in renesas-clk for v7.4.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds