Re: [PATCH 3/4] PCI: rzg3s-host: Add support for RZ/G3L SoC

[Geert Uytterhoeven]

On Tue, 25 Aug 2026 at 11:50, Biju <biju.das.au@xxxxxxxxx> wrote:
> From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
>
> Add SoC-specific data for the RZ/G3L (R9A08G046) PCIe controller and
> register its "renesas,r9a08g046-pcie" compatible string. RZ/G3L reuses
> the RZ/G3E config init/deinit callbacks and power resets, with its own
> L1-allow syscon offset and mask.
>
> Also increase the timeout in rzg3s_pcie_set_max_link_speed() to fix
> the "Failed to set max link speed" message seen on RZ/G3L.
>
> Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>

Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds