Re: [PATCH v3 08/12] clk: qcom: ipq-cmn-pll: Add EPHY-RAW clock support

[Abel Vesa]

On 26-08-14 05:48:18, Luo Jie wrote:
> The EPHY-RAW clock is an IPQ5210-specific output from the CMN PLL that
> provides the raw reference clock to the SoC-integrated Ethernet PHY
> (EPHY), which supports up to 2.5G link speed. The output frequency is
> selected via bit 10 (CMN_PLL_GEPHY_312P5M_125M_SEL) of the
> CMN_PLL_PON_CONFIG register:
> 
> - 0: 125 MHz   - for 1G/100M/10M link speed
> - 1: 312.5 MHz - for 2.5G link speed
> 
> Parent it on cmn_pll_div2, like the rest of IPQ5210's output clocks,
> for clock-tree consistency. This is functionally identical: the
> output rate is purely register-bit-selected and never depends on the
> parent rate.

So it is not a slice of the cmn_pll_div2 then. What is the actual source
of it then, in HW?