Re: [PATCH v3 06/12] clk: qcom: ipq-cmn-pll: Add PPE clock support

[Abel Vesa]

On 26-08-14 05:48:16, Luo Jie wrote:
> The PPE (packet process engine) clock is derived from the CMN PLL
> output divided by 2 and then further divided by a configurable 6-bit
> divider. It shares the CMN_PLL_NSS_PPE_FREQ_CTRL register with the
> NSS clock but uses a different field (bits [5:0]).
> 
> Register the PPE clock through the ipq_cmn_pll_regmap_div_register()
> helper introduced for the NSS clock, passing the PPE-specific field
> mask and reusing the same cmn_pll_div2 parent selection as NSS.
> 
> Signed-off-by: Luo Jie <jie.luo@xxxxxxxxxxxxxxxx>

Reviewed-by: Abel Vesa <abel.vesa@xxxxxxxxxxxxxxxx>