Re: [PATCH v3 07/12] clk: qcom: ipq-cmn-pll: Add PON reference clock support

[Abel Vesa]

On 26-08-14 05:48:17, Luo Jie wrote:
> The PON (Passive Optical Network) reference clock's parent is
> cmn_pll_div2 (CMN PLL rate / 2); it is then further divided by a
> configurable 8-bit divider (1-255). The clock supports two modes:
> 
> - UNIPHY mode (CMN_PLL_PON_MODE_SEL = 0): fixed 31.25 MHz output
> - PON mode   (CMN_PLL_PON_MODE_SEL = 1): parent_rate / divider
> 
> The clock output can be independently enabled and disabled via the
> CMN_PLL_PON_EN bit.
> 
> Signed-off-by: Luo Jie <jie.luo@xxxxxxxxxxxxxxxx>

Reviewed-by: Abel Vesa <abel.vesa@xxxxxxxxxxxxxxxx>