Re: [PATCH v16 1/2] dt-bindings: phy: qcom: Add CSI2 C-PHY/DPHY schema
From: Vladimir Zapolskiy
Date: Thu Sep 03 2026 - 13:18:31 EST
On 9/3/26 15:32, Bryan O'Donoghue wrote:
On 03/09/2026 12:53, Vladimir Zapolskiy wrote:
On 9/1/26 23:15, Bryan O'Donoghue wrote:Well, I'm not trying to describe CPHY here so I'm not claiming it is
Add a base schema for the MIPI CSI2 PHYs on Qualcomm SoCs. This PHY
supports both DPHY and CPHY operation. A special mode of DPHY operation -
called variously split-mode or combo-mode also allows for two sensors to be
connected to one PHY.
The submitted binding here describes the DPHY modes of operation only. CPHY
is left to future work.
Like I've said in v14 review, the statement above is incorrect, and it has
to be changed, for whatever reason it hasn't happened so far.
From https://lore.kernel.org/all/1e1bc17a-4c7a-4c08-b0c8-2a2ff31fe870@xxxxxxxxxx/
adequately described.
The CSIPHY IP supports C-PHY bus type, and it should be represented in
the documentation.
Right in this presented change 'bus-type' property value can be either D-PHY
or C-PHY, so even if there is no intention to describe C-PHY, it's done.
I'll reword this.
C-PHY bus type is also well described by this version of the bindings.
Suggested-by: Vladimir Zapolskiy <vladimir.zapolskiy@xxxxxxxxxx>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@xxxxxxxxxx>
---
.../bindings/phy/qcom,x1e80100-csi2-phy.yaml | 222 +++++++++++++++++++++
1 file changed, 222 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml
new file mode 100644
index 0000000000000..17de0701eb103
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml
@@ -0,0 +1,222 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/qcom,x1e80100-csi2-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm X1E80100 SoC CSI2 PHY
+
+maintainers:
+ - Bryan O'Donoghue <bod@xxxxxxxxxx>
+
+description:
+ Qualcomm MIPI CSI2 C-PHY/D-PHY combination PHY. Connects MIPI CSI2 sensors
+ to Qualcomm's Camera CSI Decoder. The PHY supports both C-PHY and D-PHY
+ modes.
+
+properties:
+ compatible:
+ const: qcom,x1e80100-csi2-phy
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 3
+
+ clock-names:
+ items:
+ - const: core
+ - const: timer
+ - const: ahb
+
+ interrupts:
+ maxItems: 1
+
+ operating-points-v2: true
+
+ opp-table:
+ type: object
+
+ power-domains:
+ items:
+ - description: Titan Top GDSC - Titan ISP Block, Global Distributed Switch Controller.
+ - description: MMCX voltage rail
+ - description: MXC or MXA voltage rail
+
+ power-domain-names:
+ items:
+ - const: top
+ - const: mmcx
+ - const: mx
+
+ vdda-0p9-supply:
+ description: Phandle to a 0.9V regulator supply to a PHY.
+
+ vdda-1p2-supply:
+ description: Phandle to 1.2V regulator supply to a PHY.
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ description:
+ Sensor input. Always present. A single sensor is described by a
+ single endpoint with the clock lane at position 0 and one to four
+ data lanes.
+
+ DPHY split mode, where two independent sensors share the same PHY,
+ is described by two endpoints, each with its own clock lane position;
+ endpoint@0 with clock-lanes = <0> and one or two data-lanes and
+ endpoint@1 with clock-lanes = <3> and one data lane.
+
+ unevaluatedProperties: false
+
+ patternProperties:
+ "^endpoint(@[01])?$":
+ $ref: /schemas/media/video-interfaces.yaml#
+ unevaluatedProperties: false
+ properties:
+ bus-type:
+ enum:
+ - 1 # MEDIA_BUS_TYPE_CSI2_CPHY
+ - 4 # MEDIA_BUS_TYPE_CSI2_DPHY
+
+ clock-lanes:
+ maxItems: 1
+
+ data-lanes:
+ minItems: 1
+ maxItems: 4
+ items:
+ minimum: 1
+ maximum: 4
+ description:
+ Data lane positions following this endpoint's clock
+ lane. Positions are a per-port logical numbering, not
+ package pad or ball positions.
+
+ required:
+ - bus-type
A review comment given to v14 is still applicable, 'bus-type' property
should be set as optional with D-PHY mode fallback.
I believe you said "could" be optional in v14 but, if you actually
_want_ it optional, I'll update this to reflect, np.
Sure, thank you.
+ - data-lanes
+ - clock-lanes
Here 'clock-lanes' is a truly optional proiperty since its value is
immutable in each endpoint, it should be removed from the list of
required properties.
Hmm.
I want to make sure clock-lanes is defined and set to the correct value.
It's not needed, the mutable properties make sense, the immutable ones
can be removed without any loss. The correctness of the propertly value
is checked by the driver in runtime.
For example clock-lanes = <2> for split mode is wrong.
If there is a wrong value of 'clock-lanes' property given, the driver will
complain, because it knows the proper value.
And if there is no 'clock-lanes' property given, the driver knows the proper
value and it reuses it rightfully.
So, there is nothing got missed, if 'clock-lanes' becomes an optional
property, as I request. A comment in the documentation can be left though.
Also 'clock-lanes' are not expected to be found in C-PHY bus type case.
Right so to both verify the property and not require it from CPHY I will
make it required only for DPHY.
By making 'clock-lanes' optional both bus type cases will be well described.
For clarity, the property is not required for D-PHY bus type mode also,
please make it optional in the next version, thank you.
--
Best wishes,
Vladimir