[PATCH 3/3] arm64: dts: realtek: Add SPI NOR flash node for RTD1625

[Yu-Chun Lin]

Add the SPI NOR flash node for the Realtek RTD1625 SoC.

Signed-off-by: Yu-Chun Lin <eleanor.lin@xxxxxxxxxxx>
---
 arch/arm64/boot/dts/realtek/kent-pinctrl.dtsi | 16 ++++++++++++
 arch/arm64/boot/dts/realtek/kent.dtsi         | 26 +++++++++++++++++++
 2 files changed, 42 insertions(+)
 create mode 100644 arch/arm64/boot/dts/realtek/kent-pinctrl.dtsi

diff --git a/arch/arm64/boot/dts/realtek/kent-pinctrl.dtsi b/arch/arm64/boot/dts/realtek/kent-pinctrl.dtsi
new file mode 100644
index 000000000000..01df3aa9254a
--- /dev/null
+++ b/arch/arm64/boot/dts/realtek/kent-pinctrl.dtsi
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2026 Realtek Semiconductor Corp.
+ */
+
+&main2_pinctrl {
+	spi_pins: spi-pins {
+		pins = "gpio_64",
+		       "gpio_65",
+		       "gpio_66",
+		       "gpio_67";
+		function = "spi";
+		realtek,drive-strength-p = <3>;
+		realtek,drive-strength-n = <2>;
+	};
+};
diff --git a/arch/arm64/boot/dts/realtek/kent.dtsi b/arch/arm64/boot/dts/realtek/kent.dtsi
index 409d46a73c91..e266d62b6527 100644
--- a/arch/arm64/boot/dts/realtek/kent.dtsi
+++ b/arch/arm64/boot/dts/realtek/kent.dtsi
@@ -5,6 +5,8 @@
  * Copyright (c) 2024 Realtek Semiconductor Corp.
  */
 
+#include <dt-bindings/clock/realtek,rtd1625-clk.h>
+#include <dt-bindings/reset/realtek,rtd1625.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 
@@ -137,6 +139,7 @@ psci: psci {
 	soc@0 {
 		compatible = "simple-bus";
 		ranges = <0x0 0x0 0x0 0x40000>, /* boot code */
+			 <0x88100000 0x0 0x88100000 0x02000000>, /* NOR flash aperture */
 			 <0x98000000 0x0 0x98000000 0xef0000>, /* rbus */
 			 <0xa0000000 0x0 0xa0000000 0x10000000>, /* PCIE */
 			 <0xff000000 0x0 0xff000000 0x200000>; /* GIC */
@@ -146,6 +149,7 @@ soc@0 {
 		rbus: bus@98000000 {
 			compatible = "simple-bus";
 			ranges = <0x0 0x98000000 0xef0000>,
+				 <0x88100000 0x88100000 0x02000000>, /* NOR flash aperture */
 				 <0xa0000000 0xa0000000 0x10000000>; /* PCIE */
 			#address-cells = <1>;
 			#size-cells = <1>;
@@ -199,6 +203,26 @@ iso_s_cc: clock-controller@146310 {
 				#reset-cells = <1>;
 			};
 
+			nor_flash: spi@14b000 {
+				compatible = "realtek,rtd1625-nor";
+				reg = <0x14b000 0x50>, <0x14bf00 0x30>, <0x88100000 0x2000000>;
+				reg-names = "ctrl", "dma", "dirmap";
+				clocks = <&cc RTD1625_CRT_CLK_EN_MD>;
+				resets = <&cc RTD1625_CRT_RSTN_MD>;
+				pinctrl-0 = <&spi_pins>;
+				pinctrl-names = "default";
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				flash@0 {
+					compatible = "jedec,spi-nor";
+					reg = <0>;
+					spi-rx-bus-width = <2>;
+					spi-tx-bus-width = <2>;
+					spi-max-frequency = <64000000>;
+				};
+			};
+
 			ve4_pinctrl: pinctrl@14e000 {
 				compatible = "realtek,rtd1625-ve4-pinctrl";
 				reg = <0x14e000 0x84>;
@@ -217,3 +241,5 @@ gic: interrupt-controller@ff100000 {
 		};
 	};
 };
+
+#include "kent-pinctrl.dtsi"
-- 
2.43.0