[RFC PATCH] arm64: dts: rockchip: add mipi csi-2 receiver nodes for the dcphys on rk3588
From: Jason Yang
Date: Fri Sep 04 2026 - 04:10:18 EST
This is test patch, contains the following 3 changes:
- raise #phy-cells to 2
- add PHY_TYPE_DSI to the dsi nodes
- add mipi csi0 and csi1
Signed-off-by: Jason Yang <jason98166@xxxxxxxxx>
---
Hi Michael, Krzysztof,
Here is the test patch for
https://lore.kernel.org/r/20260821-dcphy-rx-v1-v4-0-f1797634233d@xxxxxxxxx
I have tested imx219/ov5640 stream with csi0 and meanwhile stream on
rpi panel with dsi0, both using mipidcphy0.
Related commits:
2e177b85541d ("arm64: dts: rockchip: add mipi dcphy nodes to rk3588")
0d0947766d87 ("arm64: dts: rockchip: add dsi controller nodes on rk3588")
5052c99cf052 ("arm64: dts: rockchip: add mipi csi-2 receiver nodes to rk3588")
Best regards,
Jason
arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 76 ++++++++++++++++++-
1 file changed, 72 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
index fc1fdbfd3162..dd2bbc02f8d8 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
@@ -1516,10 +1516,18 @@ vicap_dvp: port@0 {
vicap_mipi0: port@1 {
reg = <0x1>;
+
+ vicap_mipi0_input: endpoint {
+ remote-endpoint = <&csi0_output>;
+ };
};
vicap_mipi1: port@2 {
reg = <0x2>;
+
+ vicap_mipi1_input: endpoint {
+ remote-endpoint = <&csi1_output>;
+ };
};
vicap_mipi2: port@3 {
@@ -1568,6 +1576,66 @@ vicap_mmu: iommu@fdce0800 {
status = "disabled";
};
+ csi0: csi@fdd10000 {
+ compatible = "rockchip,rk3588-mipi-csi2", "rockchip,rk3568-mipi-csi2";
+ reg = <0x0 0xfdd10000 0x0 0x10000>;
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "err1", "err2";
+ clocks = <&cru PCLK_CSI_HOST_0>;
+ phys = <&mipidcphy0 PHY_TYPE_DPHY PHY_TYPE_CSI>;
+ power-domains = <&power RK3588_PD_VI>;
+ resets = <&cru SRST_P_CSI_HOST_0>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csi0_in: port@0 {
+ reg = <0>;
+ };
+
+ csi0_out: port@1 {
+ reg = <1>;
+
+ csi0_output: endpoint {
+ remote-endpoint = <&vicap_mipi0_input>;
+ };
+ };
+ };
+ };
+
+ csi1: csi@fdd20000 {
+ compatible = "rockchip,rk3588-mipi-csi2", "rockchip,rk3568-mipi-csi2";
+ reg = <0x0 0xfdd20000 0x0 0x10000>;
+ interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "err1", "err2";
+ clocks = <&cru PCLK_CSI_HOST_1>;
+ phys = <&mipidcphy1 PHY_TYPE_DPHY PHY_TYPE_CSI>;
+ power-domains = <&power RK3588_PD_VI>;
+ resets = <&cru SRST_P_CSI_HOST_1>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csi1_in: port@0 {
+ reg = <0>;
+ };
+
+ csi1_out: port@1 {
+ reg = <1>;
+
+ csi1_output: endpoint {
+ remote-endpoint = <&vicap_mipi1_input>;
+ };
+ };
+ };
+ };
+
csi2: csi@fdd30000 {
compatible = "rockchip,rk3588-mipi-csi2", "rockchip,rk3568-mipi-csi2";
reg = <0x0 0xfdd30000 0x0 0x10000>;
@@ -1788,7 +1856,7 @@ dsi0: dsi@fde20000 {
resets = <&cru SRST_P_DSIHOST0>;
reset-names = "apb";
power-domains = <&power RK3588_PD_VOP>;
- phys = <&mipidcphy0 PHY_TYPE_DPHY>;
+ phys = <&mipidcphy0 PHY_TYPE_DPHY PHY_TYPE_DSI>;
phy-names = "dcphy";
rockchip,grf = <&vop_grf>;
status = "disabled";
@@ -1816,7 +1884,7 @@ dsi1: dsi@fde30000 {
resets = <&cru SRST_P_DSIHOST1>;
reset-names = "apb";
power-domains = <&power RK3588_PD_VOP>;
- phys = <&mipidcphy1 PHY_TYPE_DPHY>;
+ phys = <&mipidcphy1 PHY_TYPE_DPHY PHY_TYPE_DSI>;
phy-names = "dcphy";
rockchip,grf = <&vop_grf>;
status = "disabled";
@@ -3429,7 +3497,7 @@ mipidcphy0: phy@feda0000 {
<&cru SRST_P_MIPI_DCPHY0_GRF>,
<&cru SRST_S_MIPI_DCPHY0>;
reset-names = "m_phy", "apb", "grf", "s_phy";
- #phy-cells = <1>;
+ #phy-cells = <2>;
status = "disabled";
};
@@ -3445,7 +3513,7 @@ mipidcphy1: phy@fedb0000 {
<&cru SRST_P_MIPI_DCPHY1_GRF>,
<&cru SRST_S_MIPI_DCPHY1>;
reset-names = "m_phy", "apb", "grf", "s_phy";
- #phy-cells = <1>;
+ #phy-cells = <2>;
status = "disabled";
};
--
2.43.0