[PATCH v4] irqchip/gic-v3: Add Altera SoCFPGA Agilex5 GIC600 DMA32 erratum workaround
From: Adrian Ng Ho Yin
Date: Fri Sep 04 2026 - 05:34:15 EST
Agilex5 integrates GIC600 with an ACE-lite interface limited to a 32-bit
address bus, so the ITS can only access the first 4 GB of physical address
space. Add ALTERA_ERRATUM_AGILEX5 and register intel,socfpga-agilex5 on the
existing dma_32bit_impaired_platforms list.
This limitation is documented as Agilex 5 ES Device Errata 2.1.23 (825514).
Signed-off-by: Adrian Ng Ho Yin <adrian.ho.yin.ng@xxxxxxxxxx>
---
Link: https://docs.altera.com/r/docs/825514/current/agilex-5-es-device-errata-and-user-guidelines/hps-gicv3-its-and-lpi-unable-to-access-physical-memory-larger-than-32-bits-causing-msi-x-interrupt-failure
Link: https://lore.kernel.org/linux-arm-kernel/372f059069a5551ea1096015f855cc306dbd7cd4.1747368554.git.adrianhoyin.ng@xxxxxxxxxx/ # v1
Link: https://lore.kernel.org/linux-arm-kernel/6a44509ca0edaabc17e59d2e27fef1c782183456.1751618484.git.adrianhoyin.ng@xxxxxxxxxx/ # v2
Link: https://lore.kernel.org/linux-arm-kernel/20260622024945.21354-1-muhammad.nazim.amirul.nazle.asmade@xxxxxxxxxx/ # v3 (untagged)
Changes in v4:
- Rebase onto dma_32bit_impaired_platforms shared quirk (post Renesas)
- Add ALTERA_ERRATUM_AGILEX5 Kconfig and silicon-errata entry
- Cite Agilex 5 ES Device Errata 2.1.23
Changes in v3:
- Extend existing Rockchip dma32 quirk path for Agilex5
Changes in v2:
- Drop DT binding quirk; use IIDR + of_machine_is_compatible()
Documentation/arch/arm64/silicon-errata.rst | 3 +++
arch/arm64/Kconfig | 10 ++++++++++
drivers/irqchip/irq-gic-v3-its.c | 3 +++
3 files changed, 16 insertions(+)
diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/arch/arm64/silicon-errata.rst
index ac3248b9f2f3..8522ba072040 100644
--- a/Documentation/arch/arm64/silicon-errata.rst
+++ b/Documentation/arch/arm64/silicon-errata.rst
@@ -53,6 +53,9 @@ stable kernels.
| Allwinner | A64/R18 | UNKNOWN1 | SUN50I_ERRATUM_UNKNOWN1 |
+----------------+-----------------+-----------------+-----------------------------+
+----------------+-----------------+-----------------+-----------------------------+
+| Altera | SoCFPGA Agilex5 | 2.1.23 | ALTERA_ERRATUM_AGILEX5 |
++----------------+-----------------+-----------------+-----------------------------+
++----------------+-----------------+-----------------+-----------------------------+
| Ampere | AmpereOne | AC03_CPU_38 | AMPERE_ERRATUM_AC03_CPU_38 |
+----------------+-----------------+-----------------+-----------------------------+
| Ampere | AmpereOne | AC03_CPU_57 | N/A |
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index b5a51b0ef944..e3afb591db68 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -418,6 +418,16 @@ menu "Kernel Features"
menu "ARM errata workarounds via the alternatives framework"
+config ALTERA_ERRATUM_AGILEX5
+ bool "Altera Agilex5: GIC600 can not access physical addresses higher than 4GB"
+ default y
+ help
+ The Altera SoCFPGA Agilex5 GIC600 SoC integration has ACE-lite
+ addressing limited to the first 32bit of physical address space.
+ This is documented as Agilex 5 ES Device Errata 2.1.23 (825514).
+
+ If unsure, say Y.
+
config AMPERE_ERRATUM_AC03_CPU_38
bool "AmpereOne: AC03_CPU_38: Certain bits in the Virtualization Translation Control Register and Translation Control Registers do not follow RES0 semantics"
default y
diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index e9807af23537..111cbe484de9 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -4895,6 +4895,9 @@ static bool __maybe_unused its_enable_quirk_hip09_162100801(void *data)
}
static const char * const dma_32bit_impaired_platforms[] = {
+#ifdef CONFIG_ALTERA_ERRATUM_AGILEX5
+ "intel,socfpga-agilex5",
+#endif
#ifdef CONFIG_RENESAS_ERRATUM_GEN4GICITS1
"renesas,r8a779f0",
"renesas,r8a779g0",
--
2.49.GIT