Re: [PATCH v4] clk: spacemit: k3: add CPU PLL rate tables

[Yixun Lan]

Hi Anirudh,

On 11:41 Sat 05 Sep     , Anirudh Srinivasan wrote:
> Hi Troy,
> 
..
> >  drivers/clk/spacemit/ccu-k3.c | 96 +++++++++++++++++++++++++++++++++++++++++++
> >  1 file changed, 96 insertions(+)
> >
> 
> On a recently new K3 board (shipped with OpenSBI/U-boot dated
> end of July), I was seeing upstream kernel boot hang after IMSIC
> initialization. Some logging indicated that it was hanging around the
> clock controller initializations (k3_ccu_driver_init).
> 
> On a board running older U-boot/OpenSBI from May, I originally didn't
> observe this hang, but doing multiple repeated boots showed a rare
> instance of this hang happening. Some changes were added to OpenSBI in 
> this period (end of June) that trap clock controller registers to M 
> Mode and handle reads/writes there.
> 
> Yixun pointed me to this patch, and it seems to fix the boot hang on 
> the board runner newer OpenSBI. I think this avoids some kind of a 
> race condition with disabling/re-enabling a PLL that the clock driver
> does. I'm finding it a bit hard to explain/understand what exactly it
> the reason though.
> 
..
> Yixun, could this patch get added in soon?
> 
Let's wait a bit, the patch itself do solve the problem, but Aurelien
and me still have some minor concern, see other post in this thread

Although the problem is a combination of vendor firmware + upstream kernel,
but it will affect quite widely and probably last for quite long time, so I
think it would warrant a Fix tag and back port to old stable versions..

> Tested-by: Anirudh Srinivasan <asrinivasan@xxxxxxxxxxxxxxxxxxx>
> 
Thanks for the testing

-- 
Yixun Lan (dlan)