Re: [PATCH v3] PCI: rcar-gen4: Limit Max_Read_Request_Size and Max_Payload_Size to 256 Bytes

[Rong Zhang]

Hi Marek,

On Fri, 2026-09-04 at 23:53 +0200, Marek Vasut wrote:
> On 9/4/26 7:42 PM, Rong Zhang wrote:
> 
> Hello everyone,
> 
> > > > In light of the last paragraph above, that the MRRS has to be limited also
> > > > on all devices downstream of this particular controller, I would like to ask
> > > > -- does the Loongson controller have the same limitation or not ? If not,
> > > > then I would argue this quirk should be isolated to this controller variant
> > > > ; else, I am happy to start on the core patches.
> > 
> > ACK. I agreed that it should make our life easier.
> > 
> > > 
> > > I don't know if we'll get a real answer for Loongson (there's no
> > > maintainer listed for it, hint hint :)),
> > > 
> > 
> > (+CC Jiaxun)
> > 
> > The driver was introduced by Jiaxun without updating MAINTAINERS. I guess
> > he'd be willing to be listed as a maintainer.
> > 
> > I don't work for Loongson, but I do maintain several MIPS-based Loongson
> > devices for the Golang community with my colleagues and personally own a
> > MIPS-based Loongson-LS3A4000-7A1000-NUC-SE mini PC. I do some PCIe
> > experiments on it from time to time for fun. So I am OK if someone wants
> > to list me as a maintainer or reviewer :)
> > 
> > > but my guess is that it does
> > > apply to all devices downstream of the Loongson controller.
> > 
> > I believe this is the case. Maybe Jiaxun can shed a light on it too.
> > 
> > Just checked the kmsg log from April, the firmware seemed to only clamp
> > MRRS for devices directly connected to the root ports. IOW, it seemed to
> > only clamp MRRS for the upstream port of a PCIe switch, so
> > loongson_set_min_mrrs_quirk() had to fix up downstream ports.
> > 
> > If you need more information I can do some more experiments with the PCIe
> > switch card.
> 
> Please look at the commit message [1] , that lists the exact test and 
> the PCIe NVMe SSD which triggers the data corruption (let me know if 
> something is unclear). I think any PCIe NVMe SSD which is non-HMB with 
> MRRS on the SSD size that is > MRRS on the controller side will trigger 
> this issue too. 
> 

Unfortunately I don't have any non-HMB NVMe SSD, and it's unlikely I'll
get one anytime soon due to the crazy price. Before the AI supply chain
crisis, I bought several NVMe SSDs, but I chose HMB ones as they generate
less heat and consume less electricity.

> If you could reproduce it on the Loongson, then yes, it 
> is affected. You might have to disable the current MRRS workaround in 
> the Loongson PCIe driver though as it might hide the issue.

Due to the lack of non-HMB NVMe SSDs, I can't reproduce the exact same
issue. Theoretically I may try to mess around with the AHCI controller
(see the mentioned commit below) by manually overriding MRRS, as my
device's firmware already clamps it. We will see...

The firmware of many Loongson devices (except for some MIPS-based ones,
see the commit message of commit ef61a0405742 ("PCI: loongson: Limit MRRS
to 256")) already clamps MRRS for most PCIe devices, which has proven
that the 7A1000/7A2000 chipset does need the MRRS quirk. Therefore, you
can just go ahead with preparing the core patches without the need of
waiting for my test result. It seems that your approach is not going to
change the current fixup effects in a significant way, so it should be
fine.

> 
> Thank you for your help !
> 

Thanks,
Rong

> +CC NXP, because they have similar controller on MX95 (and others, but 
> the MX95 is closest to this I think)
> 
> [1] 
> https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=37ca1997d2eeec86ad065008d6387fd15d18934c