Re: [PATCH v3 03/12] phy: qualcomm: qcom-uniphy-pcie-28lp: Convert to PCIe/USB3 combo PHY driver

[Manivannan Sadhasivam]

On Tue, Aug 25, 2026 at 04:37:20PM +0400, George Moussalem via B4 Relay wrote:
> From: George Moussalem <george.moussalem@xxxxxxxxxxx>
> 
> This PHY found in IPQ5332 and IPQ5018 SoCs is actually a multi-purpose
> PCIe/USB3 combo PHY. The driver was initially created for PCIe PHY
> support only. As such, rename the driver and generalize function and
> struct names to reflect that it is a PCIe and USB3 combo PHY driver so
> that USB3 support can be added in subsequent patches.
> 
> Signed-off-by: George Moussalem <george.moussalem@xxxxxxxxxxx>
> ---
>  drivers/phy/qualcomm/Kconfig                       | 24 +++---
>  drivers/phy/qualcomm/Makefile                      |  2 +-
>  ...cie-28lp.c => phy-qcom-uniphy-pcie-usb3-28lp.c} | 87 +++++++++++-----------
>  3 files changed, 55 insertions(+), 58 deletions(-)
> 
> diff --git a/drivers/phy/qualcomm/Kconfig b/drivers/phy/qualcomm/Kconfig
> index d910a5d1a1ac..6872aa919cf2 100644
> --- a/drivers/phy/qualcomm/Kconfig
> +++ b/drivers/phy/qualcomm/Kconfig
> @@ -155,19 +155,6 @@ config PHY_QCOM_M31_USB
>  	  management. This driver is required even for peripheral only or
>  	  host only mode configurations.
>  
> -config PHY_QCOM_UNIPHY_PCIE_28LP
> -	bool "PCIE UNIPHY 28LP PHY driver"
> -	depends on ARCH_QCOM
> -	depends on COMMON_CLK
> -	depends on HAS_IOMEM
> -	depends on OF
> -	select GENERIC_PHY
> -	help
> -	  Enable this to support the PCIe UNIPHY 28LP phy transceiver that
> -	  is used with PCIe controllers on Qualcomm IPQ5332 chips. It
> -	  handles PHY initialization, clock management required after
> -	  resetting the hardware and power management.
> -
>  config PHY_QCOM_M31_EUSB
>  	tristate "Qualcomm M31 eUSB2 PHY driver support"
>  	depends on USB && (ARCH_QCOM || COMPILE_TEST)
> @@ -178,6 +165,17 @@ config PHY_QCOM_M31_EUSB
>  	  up of the associated USB repeater that is paired with the eUSB2
>  	  PHY.
>  
> +config PHY_QCOM_UNIPHY_PCIE_USB3_28LP
> +	bool "Qualcomm IPQ5332 UNIPHY PCIe USB3 28LP PHY driver"
> +	depends on OF && (ARCH_QCOM || COMPILE_TEST)
> +	select GENERIC_PHY
> +	select MFD_SYSCON
> +	help
> +	  Enable this to support the Qualcomm USB Super-Speed UNIPHY transceiver
> +	  that is used on Qualcomm IPQ5018 and IPQ5332 SoCs with DWC3 USB core.

This statement gives the impression that this driver is only used with DWC3 USB,
which is not the case.

> +	  It handles PHY initialization, clock management required after
> +	  resetting the hardware and power management.
> +
>  config PHY_QCOM_USB_HS
>  	tristate "Qualcomm USB HS PHY module"
>  	depends on USB_ULPI_BUS
> diff --git a/drivers/phy/qualcomm/Makefile b/drivers/phy/qualcomm/Makefile
> index 8bf887d58ee4..6e2e9737e387 100644
> --- a/drivers/phy/qualcomm/Makefile
> +++ b/drivers/phy/qualcomm/Makefile
> @@ -18,7 +18,7 @@ obj-$(CONFIG_PHY_QCOM_QMP_USB_LEGACY)	+= phy-qcom-qmp-usb-legacy.o
>  
>  obj-$(CONFIG_PHY_QCOM_QUSB2)		+= phy-qcom-qusb2.o
>  obj-$(CONFIG_PHY_QCOM_EUSB2_REPEATER)	+= phy-qcom-eusb2-repeater.o
> -obj-$(CONFIG_PHY_QCOM_UNIPHY_PCIE_28LP)	+= phy-qcom-uniphy-pcie-28lp.o
> +obj-$(CONFIG_PHY_QCOM_UNIPHY_PCIE_USB3_28LP)	+= phy-qcom-uniphy-pcie-usb3-28lp.o

Changing the module name is an ABI break. But since this driver is only used by
a couple of IPQ SoCs, breakage is not a concern I guess.

- Mani

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