[PATCH net-next v12 2/9] dt-bindings: net: lan9645x: add LAN9645X switch bindings
From: Jens Emil Schulz Østergaard
Date: Tue Sep 08 2026 - 03:50:34 EST
Add bindings for LAN9645X switch. We use a fallback compatible for the
smallest SKU microchip,lan96455s-switch. The last digit of the part number
is the number of usable front ports and the letter is the feature set.
The switch is a child of an externally controlled parent that hands out
one regmap per register target, so reg and reg-names describe the target
layout the way mscc,vsc7514-switch.yaml does for the equivalent
mscc,vsc7512-switch node. That binding, and the mfd parent it hangs off
in mscc,ocelot.yaml, is the model this driver and its parent follow.
rx/tx-internal-delay-ps is used to model a direct MAC to MAC fixed link,
using RGMII, where exactly one of them must supply the delay.
Documentation/networking/phy.rst describes plain rgmii as the mode where
the MAC or the PCB adds the delay rather than the PHY.
Reviewed-by: Steen Hegelund <Steen.Hegelund@xxxxxxxxxxxxx>
Signed-off-by: Jens Emil Schulz Østergaard <jensemil.schulzostergaard@xxxxxxxxxxxxx>
---
Changes in v12:
- Remove Rob's Reviewed-by
- Match both the port@ and ethernet-port@ spellings, so the per port
constraints apply. dsa.yaml accepts either, and the local pattern only
matched the long form.
- Allow 0 as well as 2000 for rx/tx-internal-delay-ps, matching what the
driver accepts, and restrict them to those two values on RGMII ports.
- Constrain the ethernet-ports node the way renesas,rzn1-a5psw.yaml does,
with additionalProperties instead of a local dsa-port.yaml $ref.
- Put the example properties in canonical order, so dt-check-style
--mode=strict is clean.
- Describe the switch register targets in reg, with a matching reg-names,
following mscc,vsc7514-switch.yaml.
- Document the default of rx/tx-internal-delay-ps, as
microchip,lan937x.yaml does.
- Describe the SKU naming in the binding description.
Changes in v5:
- No changes.
Changes in v4:
- No changes.
Changes in v3:
- remove additionalProperties: true
- remove unnecessary | from description
- change top level $ref to dsa.yaml#/$defs/ethernet-ports
- use ethernet-ports and ethernet-port
- move ethernet-ports under properties instead of patternProperties
- move unevaluatedProperties: false after $ref
- update example to use ethernet-ports and ethernet-port
Changes in v2:
- rename file to microchip,lan96455s-switch.yaml
- remove led vendor property
- add {rx,tx}-internal-delay-ps for rgmii delay
- remove labels from example
- remove container node from example
---
.../net/dsa/microchip,lan96455s-switch.yaml | 179 +++++++++++++++++++++
MAINTAINERS | 1 +
2 files changed, 180 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/dsa/microchip,lan96455s-switch.yaml b/Documentation/devicetree/bindings/net/dsa/microchip,lan96455s-switch.yaml
new file mode 100644
index 000000000000..21affce218c2
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/dsa/microchip,lan96455s-switch.yaml
@@ -0,0 +1,179 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/dsa/microchip,lan96455s-switch.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip LAN9645x Ethernet switch
+
+maintainers:
+ - Jens Emil Schulz Østergaard <jensemil.schulzostergaard@xxxxxxxxxxxxx>
+
+description: |
+ The LAN9645x switch is a multi-port Gigabit AVB/TSN Ethernet switch with
+ five integrated 10/100/1000Base-T PHYs. In addition to the integrated PHYs,
+ it supports up to 2 RGMII/RMII, up to 2 BASE-X/SERDES/2.5GBASE-X and one
+ Quad-SGMII interfaces.
+
+ The part number encodes the SKU. The last digit is the number of usable
+ front ports, 5, 7 or 9. The letter is the feature set, f for full and s for
+ standard, where full adds HSR, PRP, TAS, frame preemption and PSFP.
+
+properties:
+ compatible:
+ oneOf:
+ - enum:
+ - microchip,lan96455s-switch
+ - items:
+ - enum:
+ - microchip,lan96455f-switch
+ - microchip,lan96457f-switch
+ - microchip,lan96459f-switch
+ - microchip,lan96457s-switch
+ - microchip,lan96459s-switch
+ - const: microchip,lan96455s-switch
+
+ reg:
+ items:
+ - description: General configuration block target
+ - description:
+ CPU device queue system target, the register based frame injection
+ and extraction interface
+ - description: Chip top level target
+ - description: Rewriter target
+ - description: Switching engine target
+ - description: HSIO target
+ - description: Port 0 device target
+ - description: Port 1 device target
+ - description: Port 2 device target
+ - description: Port 3 device target
+ - description: Port 4 device target
+ - description: Port 5 device target
+ - description: Port 6 device target
+ - description: Port 7 device target
+ - description: Port 8 device target
+ - description: Queue system target
+ - description: Analyzer target
+
+ reg-names:
+ items:
+ - const: gcb
+ - const: qs
+ - const: chip_top
+ - const: rew
+ - const: sys
+ - const: hsio
+ - const: dev0
+ - const: dev1
+ - const: dev2
+ - const: dev3
+ - const: dev4
+ - const: dev5
+ - const: dev6
+ - const: dev7
+ - const: dev8
+ - const: qsys
+ - const: ana
+
+ ethernet-ports:
+ type: object
+ additionalProperties: true
+ patternProperties:
+ "^(ethernet-)?port@[0-8]$":
+ type: object
+ description: Ethernet switch ports
+ additionalProperties: true
+
+ allOf:
+ - if:
+ properties:
+ phy-mode:
+ contains:
+ enum:
+ - rgmii
+ - rgmii-rxid
+ - rgmii-txid
+ - rgmii-id
+ then:
+ properties:
+ rx-internal-delay-ps:
+ $ref: "#/$defs/internal-delay-ps"
+ tx-internal-delay-ps:
+ $ref: "#/$defs/internal-delay-ps"
+
+$ref: dsa.yaml#/$defs/ethernet-ports
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - ethernet-ports
+
+unevaluatedProperties: false
+
+$defs:
+ internal-delay-ps:
+ description:
+ Disable the delay line using 0 ps, or enable the 2000 ps delay. The
+ delay line is not tunable, so no other phase can be selected.
+ enum: [0, 2000]
+ default: 0
+
+examples:
+ - |
+ ethernet-switch@4000 {
+ compatible = "microchip,lan96459f-switch", "microchip,lan96455s-switch";
+ reg = <0x4000 0x244>, <0x8000 0x4c>, <0x10000 0x134>,
+ <0x18000 0x1910>, <0x2c000 0x12d4>, <0x30000 0xe4>,
+ <0x38000 0xb8>, <0x3c000 0xb8>, <0x40000 0xb8>,
+ <0x44000 0xb8>, <0x48000 0xb8>, <0x4c000 0xb8>,
+ <0x50000 0xb8>, <0x54000 0xb8>, <0x58000 0xb8>,
+ <0x100000 0xa000>, <0x140000 0x7468>;
+ reg-names = "gcb", "qs", "chip_top", "rew", "sys", "hsio", "dev0",
+ "dev1", "dev2", "dev3", "dev4", "dev5", "dev6", "dev7",
+ "dev8", "qsys", "ana";
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethernet-port@0 {
+ reg = <0>;
+ phy-handle = <&cuphy0>;
+ phy-mode = "gmii";
+ };
+
+ ethernet-port@1 {
+ reg = <1>;
+ phy-handle = <&cuphy1>;
+ phy-mode = "gmii";
+ };
+
+ ethernet-port@2 {
+ reg = <2>;
+ phy-handle = <&cuphy2>;
+ phy-mode = "gmii";
+ };
+
+ ethernet-port@3 {
+ reg = <3>;
+ phy-handle = <&cuphy3>;
+ phy-mode = "gmii";
+ };
+
+ ethernet-port@7 {
+ reg = <7>;
+ ethernet = <&cpu_host_port>;
+ phy-mode = "rgmii";
+ rx-internal-delay-ps = <2000>;
+ tx-internal-delay-ps = <2000>;
+
+ fixed-link {
+ full-duplex;
+ pause;
+ speed = <1000>;
+ };
+ };
+ };
+ };
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index 967b098d32d9..042431460bb9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -17798,6 +17798,7 @@ M: Jens Emil Schulz Østergaard <jensemil.schulzostergaard@xxxxxxxxxxxxx>
M: UNGLinuxDriver@xxxxxxxxxxxxx
L: netdev@xxxxxxxxxxxxxxx
S: Maintained
+F: Documentation/devicetree/bindings/net/dsa/microchip,lan96455s-switch.yaml
F: include/linux/dsa/lan9645x.h
F: net/dsa/tag_lan9645x.c
--
2.52.0