[PATCH v4 01/13] dt-bindings: phy: qcom,ipq5332-uniphy-pcie: Document the IPQ5018 USB3 PHY

[George Moussalem via B4 Relay]

From: George Moussalem <george.moussalem@xxxxxxxxxxx>

Describe the USB3 PHY found in the IPQ5018 SoC, so add the compatible
string for it as well as the required resources (clocks and resets).

The PCIe and USB physical pads are muxed and selection is done via a
control register in TCSR. By default, PCIe mode is selected, hence make
the property for USB mux selection required.

In addition, the PHY requires a 5V supply for USB3 mode operation.

Signed-off-by: George Moussalem <george.moussalem@xxxxxxxxxxx>
---
 .../bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml | 44 ++++++++++++++++++++--
 1 file changed, 41 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml
index 6e9df81441e9..f59fa4e88866 100644
--- a/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml
@@ -4,7 +4,7 @@
 $id: http://devicetree.org/schemas/phy/qcom,ipq5332-uniphy-pcie-phy.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
-title: Qualcomm UNIPHY PCIe 28LP PHY
+title: Qualcomm UNIPHY PCIe and USB3 28LP PHY
 
 maintainers:
   - Nitheesh Sekar <quic_nsekar@xxxxxxxxxxx>
@@ -17,6 +17,7 @@ properties:
   compatible:
     enum:
       - qcom,ipq5018-uniphy-pcie-phy
+      - qcom,ipq5018-uniphy-usb3-phy
       - qcom,ipq5332-uniphy-pcie-phy
 
   reg:
@@ -27,9 +28,24 @@ properties:
     maxItems: 2
 
   resets:
-    minItems: 2
+    minItems: 1
     maxItems: 3
 
+  vdd-supply:
+    description:
+      Phandle to 5V regulator supply to PHY digital circuit.
+
+  qcom,phy-usb-mux-sel:
+    description:
+      TCSR register address for mux selection control for PCIe / USB3 mode.
+      If the property is set, the driver will configure USB3 mux selection.
+      If not set, the setting defaults to PCIe mux selection (BIT(0) = 0).
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    items:
+      - items:
+          - description: phandle to TCSR syscon
+          - description: offset of PHY mux selection register
+
   "#phy-cells":
     const: 0
 
@@ -47,7 +63,6 @@ required:
   - resets
   - "#phy-cells"
   - "#clock-cells"
-  - num-lanes
 
 additionalProperties: false
 
@@ -67,6 +82,27 @@ allOf:
           items:
             - description: phy reset
             - description: cfg reset
+      required:
+        - num-lanes
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,ipq5018-uniphy-usb3-phy
+    then:
+      properties:
+        clocks:
+          items:
+            - description: usb3 pipe clock
+            - description: usb3 cfg ahb clock
+        resets:
+          items:
+            - description: usb3 phy reset
+      required:
+        - vdd-supply
+        - qcom,phy-usb-mux-sel
 
   - if:
       properties:
@@ -85,6 +121,8 @@ allOf:
             - description: phy reset
             - description: ahb reset
             - description: cfg reset
+      required:
+        - num-lanes
 
 examples:
   - |

-- 
2.53.0