Re: [PATCH v20 7/9] cxl: Add port and dport identifiers to CXL AER trace events

[Jonathan Cameron]

On Wed, 2 Sep 2026 08:39:31 -0500
Terry Bowman <terry.bowman@xxxxxxx> wrote:

> From: Dan Williams <djbw@xxxxxxxxxx>
> 
> Pass struct cxl_port * and struct cxl_dport * to the cxl_aer_* trace events
> instead of a plain struct device * derived at the caller. The trace event
> helpers then derive the right strings for Endpoints, Switch Ports, Root
> Ports, and RCH Downstream Ports consistently across the CPER and native AER
> paths.
> 
> The unified cxl_aer_* events keep "memdev" as the legacy field (Endpoint
> events populate it with the memdev name; non-Endpoint events emit
> memdev="") and add new "port" and "dport" string fields populated for all
> CXL device classes. Updated userspace can key off "port" and "dport"
> without a parallel set of events.
> 
> Remove the separate cxl_port_aer_uncorrectable_error and
> cxl_port_aer_correctable_error trace events. All CXL AER events now use the
> unified cxl_aer_* events with port and dport fields.
> 
> Rework cxl_cper_handle_prot_err() to use find_cxl_port_by_dev() and the
> unified trace helpers, replacing the per-port-type branching and
> bus_find_device() memdev lookup.
> 
> The TP_printk format string places "port=%s dport=%s" between "memdev=%s"
> and "host=%s", changing the text-mode field order from the pre-patch output.
> This does not affect consumers such as rasdaemon that use libtraceevent to
> parse fields by name rather than by fixed text position.
> 
> For non-Endpoint events (Switch Port, Root Port, RCH Dport), "memdev" is
> empty and "port"/"dport" carry the topology information.
> 
> CPER: trace firmware-supplied protocol errors even when the host device is
> unbound; the record is self-contained in ras_cap and reads no MMIO. Keep
> the host lock only to serialize the dport lookup against teardown.
> 
> Below are examples of the different CXL devices' error trace logs
> after this patch:
> 
>      ---------------------
>      | CXL RP - 0C:00.0  |
>      ---------------------
>                |
>      ---------------------
>      | CXL USP - 0D:00.0 |
>      ---------------------
>                |
>      --------------------
>      | CXL DSP - 0E:00.0 |
>      --------------------
>                |
>      ---------------------
>      | CXL EP - 0F:00.0  |
>      ---------------------
> 
> Root Port:
> cxl_aer_correctable_error: memdev= port=port1 dport=0000:0c:00.0 \
>    host=pci0000:0c serial=0: status: 'Memory Data ECC Error'
> 
> cxl_aer_uncorrectable_error: memdev= port=port1 dport=0000:0c:00.0 \
>    host=pci0000:0c serial=0: status: 'Cache Address Parity Error'  \
>    first_error: 'Cache Address Parity Error'
> 
> Upstream Switch Port:
> cxl_aer_correctable_error: memdev= port=port2 dport= host=0000:0d:00.0 \
>    serial=0: status: 'Memory Data ECC Error'
> 
> UCE NA - Upstream Switch Port UCE's are handled in the portdrv driver's
> PCI AER callbacks that are not CXL aware.
> 
> Downstream Switch Port:
> cxl_aer_correctable_error: memdev= port=port2 dport=0000:0e:00.0 \
>    host=0000:0d:00.0 serial=0: status: 'Memory Data ECC Error'
> 
> cxl_aer_uncorrectable_error: memdev= port=port2 dport=0000:0e:00.0 \
>    host=0000:0d:00.0 serial=0: status: 'Cache Address Parity Error' \
>    first_error: 'Cache Address Parity Error'
> 
> RCH Downstream Port (RCD attached under a host bridge, no switch):
> cxl_aer_correctable_error: memdev= port=root0 dport=pci0000:0c \
>    host=pci0000:0c serial=0: status: 'Memory Data ECC Error'
> 
> cxl_aer_uncorrectable_error: memdev= port=root0 dport=pci0000:0c \
>    host=pci0000:0c serial=0: status: 'Cache Address Parity Error' \
>    first_error: 'Cache Address Parity Error'
> 
> For RCH topologies, both correctable and uncorrectable protocol errors
> were previously traced against the memdev via the cxl_aer_* events with
> memdev populated. They now emit memdev="" with the RCH Downstream Port
> carried in the "dport" field (dport->dport_dev, the host bridge) and the
> host bridge in "host". Consumers that keyed RCH errors off "memdev" must
> key off "dport" instead.
> 
> Endpoint:
> cxl_aer_uncorrectable_error: memdev=mem1 port=endpoint4 dport= \
>    host=0000:0f:00.0 serial=0: status: 'Cache Address Parity Error' \
>    first_error: 'Cache Address Parity Error'
> 
> cxl_aer_correctable_error: memdev=mem1 port=endpoint4 dport= host=0000:0f:00.0 \
>    serial=0: status: 'Memory Data ECC Error'
> 
> Co-developed-by: Terry Bowman <terry.bowman@xxxxxxx>
> Signed-off-by: Terry Bowman <terry.bowman@xxxxxxx>
> Signed-off-by: Dan Williams <djbw@xxxxxxxxxx>

A trivial 'maybe it looks nicer like this' suggestion inline.
Feel free to ignore.
Reviewed-by: Jonathan Cameron <jonathan.cameron@xxxxxxxxxxxxxxxx>

> diff --git a/drivers/cxl/core/trace.c b/drivers/cxl/core/trace.c
> index 7f2a9dd0d0e3f..df42d119c53dd 100644
> --- a/drivers/cxl/core/trace.c
> +++ b/drivers/cxl/core/trace.c
> @@ -2,7 +2,42 @@
>  /* Copyright(c) 2022 Intel Corporation. All rights reserved. */
>  
>  #include <cxl.h>
> +#include <cxlmem.h>
>  #include "core.h"
>  
> +const char *cxl_trace_memdev_name(struct cxl_port *port)
> +{
> +	if (is_cxl_endpoint(port)) {
> +		struct cxl_memdev *cxlmd = to_cxl_memdev(port->uport_dev);
> +
> +		return dev_name(&cxlmd->dev);

Similar to below if you make that change.

> +	}
> +
> +	return "";
> +}
> +
> +const char *cxl_trace_host_name(struct cxl_port *port)
> +{
> +	if (is_cxl_endpoint(port)) {
> +		struct cxl_memdev *cxlmd = to_cxl_memdev(port->uport_dev);
> +
> +		return dev_name(cxlmd->dev.parent);

		return dev_name(to_cxl_memdev(port->uport_dev)->dev.parent);

Maybe that's too ugly though.

> +	}
> +
> +	return dev_name(port->uport_dev);
> +}