Re: [PATCH] mmc: sdhci-pxav3: disable clock inversion for SD HS cards

[Adrian Hunter]

On 01/09/2026 03:38, Rosen Penev wrote:
> The SDIO3 Configuration register branch of pxav3_set_uhs_signaling()
> only clears the clock-inversion and feedback-clock bits for
> MMC_TIMING_MMC_HS.  As a result, MMC_TIMING_SD_HS (ordinary SD High
> Speed) falls through to the default case, which sets SDIO3_CONF_CLK_INV
> and leaves the feedback clock cleared.
> 
> According to erratum FE-2946959, clock inversion is only needed for
> slow frequencies when the card hold-time requirement is high and is not
> required nor desirable for high-speed modes.  SD High Speed runs at 50
> MHz, so the same timing argument that applies to MMC High Speed holds.
> Treat MMC_TIMING_SD_HS the same as MMC_TIMING_MMC_HS and clear the
> clock-inversion and feedback-clock bits for both.
> 
> Assisted-by: opencode:big-pickle
> Signed-off-by: Rosen Penev <rosenp@xxxxxxxxx>

Acked-by: Adrian Hunter <adrian.hunter@xxxxxxxxx>

> ---
>  drivers/mmc/host/sdhci-pxav3.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/mmc/host/sdhci-pxav3.c b/drivers/mmc/host/sdhci-pxav3.c
> index db9dfa92cb57..9e6703e005e2 100644
> --- a/drivers/mmc/host/sdhci-pxav3.c
> +++ b/drivers/mmc/host/sdhci-pxav3.c
> @@ -284,7 +284,8 @@ static void pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs)
>  		    uhs == MMC_TIMING_UHS_DDR50) {
>  			reg_val &= ~SDIO3_CONF_CLK_INV;
>  			reg_val |= SDIO3_CONF_SD_FB_CLK;
> -		} else if (uhs == MMC_TIMING_MMC_HS) {
> +		} else if (uhs == MMC_TIMING_MMC_HS ||
> +			   uhs == MMC_TIMING_SD_HS) {
>  			reg_val &= ~SDIO3_CONF_CLK_INV;
>  			reg_val &= ~SDIO3_CONF_SD_FB_CLK;
>  		} else {