[PATCH v8 4/4] phy: ti-pipe3: Fix clock leaks in init/exit error paths

[Hongling Zeng]

Two paths return without disabling the clocks that ti_pipe3_init()
has just enabled, leaking clock enable references:

1. In ti_pipe3_init(), when regmap_update_bits() fails for PCIe mode,
   the function returns the error without calling
   ti_pipe3_disable_clocks(). The clocks stay permanently enabled
   since the PHY framework won't invoke the .exit callback on init
   failure.

2. In ti_pipe3_exit(), when the PHY is in SATA mode without
   dpll_reset_syscon, the function returns 0 early to avoid powering
   down the SATA DPLL (Errata i783), which also skips the
   ti_pipe3_disable_clocks() at the end of the function. Every
   init/exit cycle therefore leaks the clock enable reference taken
   in ti_pipe3_init().

Fix both by adding the missing ti_pipe3_disable_clocks() calls,
consistent with how the DPLL program error path handles cleanup.

Fixes: 234738ea3390 ("phy: ti-pipe3: move clk initialization to a separate function")
Fixes: 0a0830feb2ad ("phy: ti-pipe3: fix suspend")
Cc: stable@xxxxxxxxxxxxxxx
Reported-by: Sashiko AI <sashiko@xxxxxxxxxx>
Closes: https://lore.kernel.org/all/20260518023657.41852C2BCB0@xxxxxxxxxxxxxxx/
Signed-off-by: Hongling Zeng <zenghongling@xxxxxxxxxx>
---
Change in v8:
 - Expand commit message to document the SATA exit-path clock leak
   and add its own Fixes tag.

Change in v7:
 -Restore the original `return ret` in the SATA PLL-locked init path.
---
 drivers/phy/ti/phy-ti-pipe3.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/phy/ti/phy-ti-pipe3.c b/drivers/phy/ti/phy-ti-pipe3.c
index fdd81c935e5f..0d4a49a3f0c7 100644
--- a/drivers/phy/ti/phy-ti-pipe3.c
+++ b/drivers/phy/ti/phy-ti-pipe3.c
@@ -518,6 +518,8 @@ static int ti_pipe3_init(struct phy *x)
 		val = 0x96 << OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT;
 		ret = regmap_update_bits(phy->pcs_syscon, phy->pcie_pcs_reg,
 					 PCIE_PCS_MASK, val);
+		if (ret)
+			ti_pipe3_disable_clocks(phy);
 		return ret;
 	}
 
@@ -555,8 +557,10 @@ static int ti_pipe3_exit(struct phy *x)
 	/* If dpll_reset_syscon is not present we wont power down SATA DPLL
 	 * due to Errata i783
 	 */
-	if (phy->mode == PIPE3_MODE_SATA && !phy->dpll_reset_syscon)
+	if (phy->mode == PIPE3_MODE_SATA && !phy->dpll_reset_syscon) {
+		ti_pipe3_disable_clocks(phy);
 		return 0;
+	}
 
 	/* PCIe doesn't have internal DPLL */
 	if (phy->mode != PIPE3_MODE_PCIE) {
-- 
2.25.1