Re: [PATCH v11 00/12] PCI/CXL: Add CXL reset support for Type 2 devices

[Srirangan Madhavan]

On 9/4/26 2:15 AM, Richard Cheng wrote:
> > and the kernel must have cached HDM state sufficient to validate affected
> > ranges and restore decoder programming. The reset preserves device
> > memory; it does not request CXL Reset Memory Clear.
> It seems reasonable to me, the whole approach.
> I wonder if we can document the complete reset-safety contract down ?
>
> Especially what guarantees that all CXL.mem users and functions are quiesced ?
> Besides HDM EP , what are other EP state that should be retained or restored ?
>
> I think it will make people understand the mechanism more easily.
>
> Best regards,
> Richard Cheng.
Thank you. I expanded the v12 cover letter and ABI documentation to 
describe the complete reset-safety contract, including the quiescing 
assumptions, state restoration, and limitations around memory offlining 
and mapping revocation.
--
Regards,
Srirangan