Re: [PATCH v3 3/5] PCI: qcom: Add CGC disable workaround for Nord PCIe

[Manivannan Sadhasivam]

On Wed, Sep 09, 2026 at 05:18:18PM +0530, Krishna Chaitanya Chundru wrote:
> Nord requires a workaround to address a timing convergence issue in the
> PCIe power domain. To avoid the issue, set the CORE_CLK_CGC_DIS and
> AUX_PWR_DET bits in PARF_SYS_CTRL after controller initialization.
> 

Both the subject and commit message sounds like this patch is only adding the
CGC workaround (you need to expand CGC btw), but this patch is adding Nord PCIe
controller support. So that should be the subject and CGC, l0s, no_snoop should
be documented in the commit message.

> The SLV_ACLK_CGC_DIS bit is already configured by hardware reset. This
> change adds the remaining required settings as documented in
> QCTDD11972446.

Mention that this erratum is private and not available publicly.

> 
> Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxxxxxxxx>
> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@xxxxxxxxxxxxxxxx>
> ---
>  drivers/pci/controller/dwc/pcie-qcom.c | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index b58a607b713f..b97e40fb7ec8 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -281,6 +281,7 @@ struct qcom_pcie_cfg {
>  	bool override_no_snoop;
>  	bool firmware_managed;
>  	bool no_l0s;
> +	bool cgc_dis_workaround;

'disable_cgc'

>  };
>  
>  struct qcom_pcie_perst {
> @@ -1097,11 +1098,18 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie)
>  static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie)
>  {
>  	const struct qcom_pcie_cfg *pcie_cfg = pcie->cfg;
> +	u32 val;
>  
>  	if (pcie_cfg->override_no_snoop)
>  		writel(WR_NO_SNOOP_OVERRIDE_EN | RD_NO_SNOOP_OVERRIDE_EN,
>  				pcie->parf + PARF_NO_SNOOP_OVERRIDE);
>  
> +	if (pcie_cfg->cgc_dis_workaround) {
> +		val = readl(pcie->parf + PARF_SYS_CTRL);
> +		val |= CORE_CLK_CGC_DIS | AUX_PWR_DET;
> +		writel(val, pcie->parf + PARF_SYS_CTRL);
> +	}
> +
>  	qcom_pcie_set_slot_cap(pcie->pci);
>  
>  	return 0;
> @@ -1630,6 +1638,13 @@ static const struct qcom_pcie_cfg cfg_2_9_0 = {
>  	.ops = &ops_2_9_0,
>  };
>  
> +static const struct qcom_pcie_cfg cfg_nord = {

Can you use DWC IP version instead of SoC name?

- Mani

-- 
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