Re: [PATCH v12 00/12] PCI/CXL: Add CXL reset support for Type 2 devices

[Srirangan Madhavan]

On 9/10/26 12:07 AM, Srirangan Madhavan wrote:
> v12 changes from v11 [2]:
> - Reject cxl_reset and cxl_bus reset when the PF has enabled VFs,
>    including VFs enabled after reset-method probing.
> - Require CXL Reset Memory Clear support and request memory clearing so
>    the generic PCI reset does not preserve tenant memory.
> - Cache the CXL Device DVSEC control register during early PCI discovery
>    and restore its CXL.cache and CXL.mem enable bits after CXL Reset and
>    CXL bus reset.
> - Initialize the early PCI HDM cache only from pci_bus_add_device(),
>    removing the later CXL core retry and its lifecycle locking.
> - Reapply and verify a cached HDM decoder lock after decoder restoration
>    and commit, while leaving surviving locked committed state unchanged.
> - Convert temporary early HDM-cache ownership to scoped cleanup.
> - Document the reset-safety contract, including the iomem ownership
>    requirement and the limits around memory offlining and mapping
>    revocation.

Hi Bjorn, Dave, and CXL maintainers

Based on the review feedback so far, I believe the overall design is in 
reasonable shape. I have addressed the feedback received so far in v12.
The series passes the kernel/module build checks and both cxl_reset and 
cxl_bus testing on a target system.
I would appreciate any guidance on remaining issues or additional 
changes needed to move the series further toward acceptance.
--
Regards,
Srirangan