Re: [PATCH 2/3] dt-bindings: clock: qcom: document the Nord DPRX Clock Controller
From: Taniya Das
Date: Thu Sep 10 2026 - 05:03:34 EST
On 9/9/2026 2:01 PM, Shawn Guo wrote:
> On Mon, Sep 07, 2026 at 01:56:14PM +0530, Taniya Das wrote:
>> Add bindings documentation for the Nord DisplayPort Receiver (DPRX) Clock Controller.
>>
>> Signed-off-by: Taniya Das <taniya.das@xxxxxxxxxxxxxxxx>
>> ---
>> .../bindings/clock/qcom,nord-dprxcc.yaml | 68 ++++++++++++++++++++++
>> include/dt-bindings/clock/qcom,nord-dprxcc.h | 27 +++++++++
>> 2 files changed, 95 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/clock/qcom,nord-dprxcc.yaml b/Documentation/devicetree/bindings/clock/qcom,nord-dprxcc.yaml
>> new file mode 100644
>> index 0000000000000000000000000000000000000000..fbaaad1f3db3ff67589d6201ed0e25710c044614
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/qcom,nord-dprxcc.yaml
>> @@ -0,0 +1,68 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/clock/qcom,nord-dprxcc.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Qualcomm DPRX Clock & Reset Controller on Nord
>> +
>> +maintainers:
>> + - Taniya Das <taniya.das@xxxxxxxxxxxxxxxx>
>> +
>> +description: |
>
> " |" can be dropped?
Sure.
>
>> + Qualcomm dprx clock control module provides the clocks, resets and power
>> + domains on Nord.
>
> I'm not sure it provides power domains, as the driver registers no GDSCs
> and the binding has no #power-domain-cells.
>
> Shawn
Okay, will drop this as well.
>
>> +
>> + See also:
>> + include/dt-bindings/clock/qcom,nord-dprxcc.h
>> +
>> +properties:
>> + compatible:
>> + enum:
>> + - qcom,nord-dprxcc0
>> + - qcom,nord-dprxcc1
>> +
>> + clocks:
>> + items:
>> + - description: XO clock source
>> + - description: DPRX CFG AHB clock from NWGCC
>> + - description: Sleep clock source
>> +
>> + power-domains:
>> + description:
>> + MMCX power domain.
>> + maxItems: 1
>> +
>> + required-opps:
>> + description:
>> + MMCX performance point.
>> + maxItems: 1
>> +
>> +required:
>> + - compatible
>> + - clocks
>> + - power-domains
>> + - required-opps
>> +
>> +allOf:
>> + - $ref: qcom,gcc.yaml#
>> +
>> +unevaluatedProperties: false
>> +
>> +examples:
>> + - |
>> + #include <dt-bindings/clock/qcom,nord-nwgcc.h>
>> + #include <dt-bindings/clock/qcom,rpmh.h>
>> + #include <dt-bindings/power/qcom,rpmhpd.h>
>> + clock-controller@a940000 {
>> + compatible = "qcom,nord-dprxcc0";
>> + reg = <0x0a940000 0xc000>;
>> + clocks = <&rpmhcc RPMH_CXO_CLK>,
>> + <&nwgcc NW_GCC_DPRX0_CFG_AHB_CLK>,
>> + <&sleep_clk>;
>> + power-domains = <&rpmhpd RPMHPD_MMCX>;
>> + required-opps = <&rpmhpd_opp_low_svs>;
>> + #clock-cells = <1>;
>> + #reset-cells = <1>;
>> + };
>> +...
>> diff --git a/include/dt-bindings/clock/qcom,nord-dprxcc.h b/include/dt-bindings/clock/qcom,nord-dprxcc.h
>> new file mode 100644
>> index 0000000000000000000000000000000000000000..62c26b58ebef04f05ea1dc77664c03aaad65baa4
>> --- /dev/null
>> +++ b/include/dt-bindings/clock/qcom,nord-dprxcc.h
>> @@ -0,0 +1,27 @@
>> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
>> +/*
>> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
>> + */
>> +
>> +#ifndef _DT_BINDINGS_CLK_QCOM_DPRX_CC_NORD_H
>> +#define _DT_BINDINGS_CLK_QCOM_DPRX_CC_NORD_H
>> +
>> +/* DPRX_CC clocks */
>> +#define DPRX_CC_AHB_CLK 0
>> +#define DPRX_CC_AUD_CLK 1
>> +#define DPRX_CC_AUDIO_CLK_SRC 2
>> +#define DPRX_CC_CORE_AHB_DIV_CLK_SRC 3
>> +#define DPRX_CC_CORE_AUD_DIV_CLK_SRC 4
>> +#define DPRX_CC_CORE_RCG0_CLK_SRC 5
>> +#define DPRX_CC_CORE_RCG2_CLK_SRC 6
>> +#define DPRX_CC_CORE_RCG3_CLK_SRC 7
>> +#define DPRX_CC_MDP_MEM_CLK 8
>> +#define DPRX_CC_MMCX_XO_CLK 9
>> +#define DPRX_CC_PLL0 10
>> +#define DPRX_CC_PLL1 11
>> +#define DPRX_CC_VID_MEM_CLK 12
>> +
>> +/* DPRX_CC resets */
>> +#define DPRX_CC_DPRX_BLK_BCR 0
>> +
>> +#endif
>>
>> --
>> 2.34.1
>>
>>
--
Thanks,
Taniya Das