Re: [PATCH v3 11/12] phy: phy-mtk-dp: Add PHYD Lane EN register mask to SoC data

[AngeloGioacchino Del Regno]

On 9/9/26 19:25, Manivannan Sadhasivam wrote:
> On Tue, Jul 07, 2026 at 05:42:44PM +0200, AngeloGioacchino Del Regno wrote:
> > In preparation for adding support for the eDP PHY found in newer
> > SoCs, transfer the register mask for PHYD_TX_LN_EN to SoC specific
> > data.
> >
> > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@xxxxxxxxxxxxx>
> > ---
> >   drivers/phy/mediatek/phy-mtk-dp.c | 13 +++++++++----
> >   1 file changed, 9 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/phy/mediatek/phy-mtk-dp.c b/drivers/phy/mediatek/phy-mtk-dp.c
> > index 4603f28d1466..f5aadc5fdc42 100644
> > --- a/drivers/phy/mediatek/phy-mtk-dp.c
> > +++ b/drivers/phy/mediatek/phy-mtk-dp.c
> > @@ -220,6 +220,7 @@ struct mtk_dp_phya_imp_sel {
> >    * @regs_ana_lane:  Register (layout) offsets for ana_lan
> >    * @regs_dig_glb:   Register (layout) offsets for dig_glb
> >    * @regs_dig_lane:  Register (layout) offsets for dig_lan
> > + * @mask_dig_tx_ln: Register mask for PHYD_TX_LN_EN field
> >    * @val_dig_bitrate:IP Version specific register values for Bit Rate setting
> >    * @ana_bias_r:     Internal resistance "R" Selection Settings (global)
> >    * @ana_cktx_imp:   TX Clock Impedance Selection Settings (global)
> > @@ -239,6 +240,9 @@ struct mtk_dp_phy_pdata {
> >   	const u8 *regs_dig_glb;
> >   	const u8 *regs_dig_lane;
> >   
> > +	/* Register masks */
>
> Duplicate comment. With this removed,

Sorry but I think you didn't understand what the comments are there: the kerneldoc
is used to describe the structure, of course, but the comments in between are used
as a way to describe (and kind of enforce) the order of members.

/* Register offsets */
u16 member1;
u16 member2;
....

/* Register maps */
const u8 *regs1;
const u8 *regs2;
...

/* Register masks */
u32 mask1;
u32 mask2;
....

etc.

Does that make sense now? :-)

Cheers,
Angelo


> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxxxxxxxx>
>
> - Mani