Re: [PATCH 4/5] clk: spacemit: reject rate changes to running firmware PLLs

[Yao Zi]

On Wed, Sep 09, 2026 at 10:07:04PM +0800, Troy Mitchell wrote:
> CLK_SET_RATE_GATE only protects clocks prepared through CCF. A PLL left
> running by firmware can have a zero prepare count, so this flag alone
> cannot prevent set_rate() from reprogramming a live PLL.

Would it be a better idea to simply turn off the PLL before reprogramming,
since protected by CLK_SET_RATE_GATE, re-programming never happens when
the PLL is required by downstream? This also seems to be simpler.

> Check the hardware state and reject set_rate() while either the enable
> or lock bit is set on K1 PLLs and K3 PLLAs. Propagate register read/write
> failures and reject rate requests with no table candidate. Callers must
> still move consumers away and stop the PLL before changing its rate.
> 
> Fixes: 1b72c59db0ad ("clk: spacemit: Add clock support for SpacemiT K1 SoC")
> Fixes: 3a086236c600 ("clk: spacemit: ccu_pll: add plla type clock")
> Signed-off-by: Troy Mitchell <troy.mitchell@xxxxxxxxxxxxxxxxxx>

Best regards,
Yao Zi