Re: [RFC][PATCH] arm64: dts: renesas: r8a779f0: Add GICv3 ITS and update PCIe nodes

[Marek Vasut]

Hello Den-san,

On 9/10/26 10:18 AM, Koichiro Den wrote:
> On Wed, Sep 09, 2026 at 07:58:46PM +0200, Marek Vasut wrote:
> > This SoC implements GIC600 with GICv3 ITS and PCIe host mode on this
> > SoC can use it. Add GIC ITS node into GIC node, update interrupt-map
> > and add msi-map into PCIe controller node.
> >
> > The GIC ITS does have master interface to issue transactions to RAM.
> > The interface does support cacheable transactions, however, it does
> > not support shareable attribute, because the AXI port signals are tied
> > to inactive in this implementation. Therefore, add "dma-noncoherent"
> > DT property into the GIC ITS subnode.
> >
> > The GIC redistributor does not have cacheable/shareable, therefore
> > add "dma-noncoherent" DT property into the GIC node.
> >
> > Signed-off-by: Marek Vasut <marek.vasut+renesas@xxxxxxxxxxx>
> > ---
> > Cc: Conor Dooley <conor+dt@xxxxxxxxxx>
> > Cc: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
> > Cc: Koichiro Den <den@xxxxxxxxxxxxx>
> > Cc: Krzysztof Kozlowski <krzk+dt@xxxxxxxxxx>
> > Cc: Magnus Damm <magnus.damm@xxxxxxxxx>
> > Cc: Rob Herring <robh@xxxxxxxxxx>
> > Cc: devicetree@xxxxxxxxxxxxxxx
> > Cc: linux-kernel@xxxxxxxxxxxxxxx
> > Cc: linux-renesas-soc@xxxxxxxxxxxxxxx
> > ---
> > NOTE: I am sending this as an RFC. Den-san, would you please test
> >        whether this works correctly together with your Endpoint setup?
> >        Especially whether the Host-side MSI change does not break it?
> >        Thank you for your help!
>
> Yes, I confirmed that it works fine with renesas-next-2026-09-09-v7.3-rc1
> kernel.
>
> Tested-by: Koichiro Den <den@xxxxxxxxxxxxx>

Thank you!

--
Best regards,
Marek Vasut