Re: [PATCH v4 5/9] phy: qualcomm: qmp-combo: Add v8 PCS-level drive level tables for Glymur

[Manivannan Sadhasivam]

On Tue, Sep 08, 2026 at 07:30:58PM +0530, Nabige Aala wrote:
> From: Ritesh Kumar <ritesh.kumar@xxxxxxxxxxxxxxxx>
> 
> Add PCS-level drive level tables for the Glymur (V8) DP PHY:
> - qmp_dp_v8_ln_drv_lvl_hbr3_hbr2: LN0/LN1_DRV_LVL settings for HBR3/HBR2
> - qmp_dp_v8_ln_drv_lvl_hbr_rbr: LN0/LN1_DRV_LVL settings for HBR/RBR
> - qmp_dp_v8_pre_emphasis_hbr_rbr: updated TX_EMP_POST1_LVL values for
>  HBR/RBR
> 
> Add ln_drv_lvl_hbr_rbr and ln_drv_lvl_hbr3_hbr2 pointer fields to
> qmp_phy_cfg to allow per-platform PCS drive level table selection.
> 
> Wire the new tables into glymur_usb3dpphy_cfg, replacing the previously
> used qmp_dp_v6_pre_emphasis_hbr_rbr with the corrected v8 table.
> 

Patch description doesn't explain why this change is needed, but just describes
the change. Is it fixing an issue? If so, there should be a relevant fixes tag.

- Mani

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