Re: [PATCH v7 08/17] iio: adc: ad7768: Derive output data rates

[Andy Shevchenko]

On Thu, Sep 10, 2026 at 07:36:26PM +0200, Janani Sunil wrote:
> Derive valid output data rates from the master clock, power mode and
> decimation ratio.
> 
> Replace the fixed x64 decimation and open-coded DCLK divider in
> ad7768_configure_capture() with the derived default output rate and the
> new decimation and clock-divider helpers. Select the maximum rate
> supported by the configured data interface for the initial capture
> configuration.

...

> +	freq_cfg = ad7768_find_freq_config(st, st->power_mode_idx, freq);
> +	if (!freq_cfg)
> +		return -EINVAL;
> +
> +	mclk = clk_get_rate(st->mclk);
> +	chan_per_doutx = st->chip_info->num_channels / st->datalines;
> +	if (!chan_per_doutx)
> +		return -EINVAL;
> +
> +	dclk = freq_cfg->freq_hz * AD7768_SAMPLE_SIZE * chan_per_doutx;
> +	if (dclk > mclk)
> +		return -EINVAL;
> +
> +	dclk_div = DIV_ROUND_CLOSEST(mclk, dclk);
> +
> +	/* Set the divider to the next-lowest supported power of two. */
> +	dclk_div = rounddown_pow_of_two(min(dclk_div, AD7768_MAX_DCLK_DIV));
> +
> +	switch (dclk_div) {
> +	case 1:
> +		dclk_div_reg = AD7768_INTERFACE_CFG_DCLK_DIV_1;
> +		break;
> +	case 2:
> +		dclk_div_reg = AD7768_INTERFACE_CFG_DCLK_DIV_2;
> +		break;
> +	case 4:
> +		dclk_div_reg = AD7768_INTERFACE_CFG_DCLK_DIV_4;
> +		break;
> +	case 8:
> +		dclk_div_reg = AD7768_INTERFACE_CFG_DCLK_DIV_8;
> +		break;
> +	default:
> +		return -EINVAL;
> +	}
> +
> +	return regmap_update_bits(st->regmap, AD7768_REG_INTERFACE_CFG,
> +				  AD7768_INTERFACE_CFG_DCLK_DIV_MSK,
> +				  FIELD_PREP(AD7768_INTERFACE_CFG_DCLK_DIV_MSK,
> +					     dclk_div_reg));

(Some of) this code is moved in the same series! Please, make sure it's not got
-+ in this patch. This can be achieved, exempli gratia, by creating a helper to
begin with at the proper location from the start.

-- 
With Best Regards,
Andy Shevchenko