Re: [PATCH v7 0/9] mmc: sdhci-cadence: add SD6HC support and Agilex5 enablement

[Ulf Hansson]

On Tue, Sep 1, 2026 at 8:49 PM Tanmay Kathpalia
<tanmay.kathpalia@xxxxxxxxxx> wrote:
>
> This series adds support for the Cadence SD6HC (sixth-generation) SDHCI
> controller and enables it on Altera Agilex5 SoCs.
>
> The SD6HC PHY architecture differs substantially from the SD4HC: it
> requires dedicated per-speed-mode IO cell timing parameters and a
> DLL-based delay line to achieve correct signal margins across all speed
> grades from Default Speed through HS400. These are programmed through a
> new sdhci-cadence-phy-v6.c file; shared driver infrastructure lives in
> sdhci-cadence-core.c.
>
> Note: this series depends on commit ab45ecfab540 ("dt-bindings: reset:
> altr: add COMBOPHY_RESET for Agilex5"), which is already in mainline via
> the reset tree. It is not yet in mmc/next; apply or merge that commit
> when building/testing this series on top of mmc/next. The previous v1/v2
> reset binding patch is therefore omitted from this series.
>
> Board DTS files do not enable the SMMU; that is provided by commit
> 10cf797f3f8a ("arm64: dts: socfpga: agilex5: Enable the SMMU") in the
> SoC DT tree. It is not yet in mmc/next. Apply or merge that commit when
> building/testing this series on top of mmc/next, otherwise the SMMU
> stays disabled in socfpga_agilex5.dtsi.
>
> Patch 1: DT binding
>   Adds a dedicated cdns,sd6hc.yaml binding with SD6HC compatible strings,
>   clock/reset/IOMMU constraints, and PHY timing properties.
>
> Patches 2-5: Device tree
>   Patch 2 adds the SD6HC controller node to the Agilex5 SoC DTSI as
>   sdmmc, left disabled.
>   Patch 3 enables SD card operation (4-bit, SDR104, 200 MHz) on the
>   SOCDK OOBE board with GPIO-switched IO-voltage regulation.
>   Patch 4 registers the intel,socfpga-agilex5-socdk-emmc board variant
>   in the arm/altera binding.
>   Patch 5 adds socfpga_agilex5_socdk_emmc.dts for eMMC-only operation
>   (8-bit, HS200/HS400, 1.8 V IO, 200 MHz).
>
> Patches 6-9: Driver
>   Patch 6 renames SD4HC-specific functions and structures with a "cdns4"
>   prefix to separate them from shared driver paths.
>   Patch 7 encapsulates SD4HC PHY probing in sdhci_cdns4_phy_probe() and
>   makes every of_device_id entry carry explicit platform data, removing
>   the silent fallback.
>   Patch 8 introduces the SD6HC PHY driver (sdhci-cadence-phy-v6.c): DLL
>   lock/bypass, per-speed-mode IO cell timing, tuning, and HW reset. The
>   common driver core selects between v4 and v6 PHY operations based on
>   the SDHCI specification version reported by the controller, and
>   reprograms the PHY from set_clock and set_uhs_signaling. SD6HC clocks
>   are requested by name ("ciu" and "biu").
>   Patch 9 adds the Agilex5 platform overlay under altr,agilex5-sd6hc:
>   40-bit DMA mask for the SMMU address space, quirks for
>   CAP_CLOCK_BASE_BROKEN, PRESET_VALUE_BROKEN, ACMD23_BROKEN and
>   MULTIBLOCK_READ_ACMD12, .get_max_clock set to
>   sdhci_pltfm_clk_get_max_clock, and an init hook that asserts and
>   deasserts the three named resets together, keeping exclusive ownership
>   via devm so they stay deasserted for the life of the device.
>
> Tested on Agilex5 SOCDK:
>   - SD card: Default Speed, High Speed, SDR25, SDR50, SDR104
>   - eMMC daughter board: HS200, HS400
>
> Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@xxxxxxxxxx>
>
> ---
> Changes in v7:
>

[...]

Patch 1 and 6-9 from the v7 series, applied for next, thanks!

Kind regards
Uffe