[PATCH 2/6] ARC: Emulate two-byte cmpxchg
From: Bradley Morgan
Date: Fri Sep 11 2026 - 15:36:52 EST
arc has no byte or halfword atomic memory operations, so the LLSC
arch_cmpxchg_relaxed() switch routes case 1 through cmpxchg_emu_u8()
and leaves case 2 to fall into the BUILD_BUG() default. Route case 2
through the new cmpxchg_emu_u16() instead.
The !CONFIG_ARC_HAS_LLSC arch_cmpxchg() already handles any size,
reading and writing through the typed pointer under the atomic_ops
lock, so it needs no change.
Signed-off-by: Bradley Morgan <brads@xxxxxxxxxxxxxx>
---
arch/arc/include/asm/cmpxchg.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arc/include/asm/cmpxchg.h b/arch/arc/include/asm/cmpxchg.h
index 76f43db0890f..9b48b8fe0db2 100644
--- a/arch/arc/include/asm/cmpxchg.h
+++ b/arch/arc/include/asm/cmpxchg.h
@@ -50,6 +50,9 @@
case 1: \
_prev_ = (__typeof__(*(ptr)))cmpxchg_emu_u8((volatile u8 *__force)_p_, (uintptr_t)_o_, (uintptr_t)_n_); \
break; \
+ case 2: \
+ _prev_ = (__typeof__(*(ptr)))cmpxchg_emu_u16((volatile u16 *__force)_p_, (uintptr_t)_o_, (uintptr_t)_n_); \
+ break; \
case 4: \
_prev_ = __cmpxchg(_p_, _o_, _n_); \
break; \
--
2.47.3