Re: [PATCH] drm/msm/dp: fix link bandwidth check when wide bus is enabled

[Dmitry Baryshkov]

On Wed, Aug 12, 2026 at 11:05:52AM +0100, William Bright wrote:
> msm_dp_display_mode_valid() halves the pixel clock when either YUV420 or
> wide bus is in use, then uses that halved value both for the controller
> pixel clock limit and for the DP link bandwidth check.
> 
> Only YUV420 halves the data crossing the link. Wide bus widens the
> internal DPU to DP interface to two pixels per clock, halving the
> controller clock. Every pixel is still transmitted, so the link
> bandwidth requirement remains.
> 
> As a result, modes needing up to twice the available link bandwidth pass
> validation. On the IMDT QCS8550 SBC (rev5 with CYPD6125), where DP runs
> over USB-C alt mode where only two lanes are available, 3840x2160@60 was
> accepted despite needing 9.6 Gbps against the 8.64 Gbps the link can
> carry.
> 
> Use a separate link pixel clock that is only halved for YUV420 for the
> bandwidth calculation, leaving the wide bus halving to apply solely to
> the controller pixel clock limit. With this, 4k@60 is correctly rejected
> and 4k@30 selected instead.
> 
> Fixes: df9cf852ca30 ("drm/msm/dp: account for widebus and yuv420 during mode validation")
> Assisted-by: Claude:claude-opus-5
> Signed-off-by: William Bright <william.bright@xxxxxxxxxxx>
> ---
>  drivers/gpu/drm/msm/dp/dp_display.c | 12 ++++++++++--
>  1 file changed, 10 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c
> index bc646d172abe..b2d6cb82a146 100644
> --- a/drivers/gpu/drm/msm/dp/dp_display.c
> +++ b/drivers/gpu/drm/msm/dp/dp_display.c
> @@ -756,6 +756,7 @@ enum drm_mode_status msm_dp_display_mode_valid(struct msm_dp *dp,
>  	struct msm_dp_link_info *link_info;
>  	u32 mode_rate_khz = 0, supported_rate_khz = 0, mode_bpp = 0;
>  	int mode_pclk_khz = mode->clock;
> +	int link_pclk_khz;
>  	bool is_yuv_420;
>  
>  	if (!dp || !mode_pclk_khz || !dp->connector) {
> @@ -775,6 +776,13 @@ enum drm_mode_status msm_dp_display_mode_valid(struct msm_dp *dp,
>  	if (is_yuv_420 && !msm_dp_display->panel->vsc_sdp_supported)
>  		return MODE_NO_420;
>  
> +	/*
> +	 * Only YUV 420 actually halves the link bandwidth, as wide bus only
> +	 * halves the pixel clock within the SoC, while the link bandwidth
> +	 * requirement remains the same.
> +	 */

When using Claude coding agents please ask them to trim the comments,
which are better suitable for the commit messages. This one is
completely redundant as it duplicates the code and adds no extra
information. I'll drop it while applying.

Otherwise LGTM


Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxxxxxxxx>



> +	link_pclk_khz = is_yuv_420 ? mode_pclk_khz / 2 : mode_pclk_khz;
> +
>  	if (is_yuv_420 || msm_dp_display->wide_bus_supported)
>  		mode_pclk_khz /= 2;
>  
> @@ -786,9 +794,9 @@ enum drm_mode_status msm_dp_display_mode_valid(struct msm_dp *dp,
>  		mode_bpp = default_bpp;
>  
>  	mode_bpp = msm_dp_panel_get_mode_bpp(msm_dp_display->panel,
> -			mode_bpp, mode_pclk_khz);
> +			mode_bpp, link_pclk_khz);
>  
> -	mode_rate_khz = mode_pclk_khz * mode_bpp;
> +	mode_rate_khz = link_pclk_khz * mode_bpp;
>  	supported_rate_khz = link_info->num_lanes * link_info->rate * 8;
>  
>  	if (mode_rate_khz > supported_rate_khz)
> 
> ---
> base-commit: 140b13475302601368c0cf4e193e66126a49feb3
> change-id: 20260812-msm-dp-link-bw-99255c870bc4
> 
> Best regards,
> --  
> William Bright <william.bright@xxxxxxxxxxx>
> 

-- 
With best wishes
Dmitry