[PATCH v5 0/3] DSI Controller improvements for Rockchip platforms

[Chaoyi Chen]

From: Chaoyi Chen <chaoyi.chen@xxxxxxxxxxxxxx>

This series is dedicated to enhancing the DSI controller and PHY timing
interaction, refining the lane rate calculation, and addressing the
associated hardware limitations.

Changes in v5:
- Link to v4: https://lore.kernel.org/all/20260812073002.328-1-kernel@xxxxxxxxxx/
- Change the upper bound check for target_mbps from < to <= (sashiko).

Changes in v4:
- Link to v3: https://lore.kernel.org/all/20260810034139.148-1-kernel@xxxxxxxxxx/
- Add missing RK3506 timing and the fallback path for get_timing
  (sashiko).
- Fix potential overflow and underflow issues in bandwidth
  calculation(sashiko).

Changes in v3:
- Link to v2: https://lore.kernel.org/all/20260603033532.164-1-kernel@xxxxxxxxxx/
- Rebase to Linux v7.2

Changes in v2:
- Link to v1: https://lore.kernel.org/all/20260324085838.90-1-kernel@xxxxxxxxxx/
- Fix the unit conversion for max_mbps.
- Split the lane rate calculation into a separate patch.
- Add more comment about timing config.

Chaoyi Chen (3):
  drm/rockchip: dsi: Add maximum per lane bit rate calculation
  drm/rockchip: dsi: Add dphy_get_timing support for multiple PHY types
  drm/rockchip: dsi: Relax the lane rate margin requirements

 .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c   | 72 +++++++++++++++++--
 1 file changed, 65 insertions(+), 7 deletions(-)

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2.53.0