Re: [PATCH 1/2] clk: mediatek: mt8173: fix the FHCTL DDS mask width

[AngeloGioacchino Del Regno]

On 9/12/26 08:40, Ryan Brue wrote:
> MT8173's hoppable PLLs have pcwbits = 21, so the FHCTL DDS field is bits
> 20:0, but FH() declares .dds_mask = GENMASK(21, 0). Bit 21 of FHCTL_MON is
> a status bit that comes up once a hop has settled, and new_dds from
> mtk_pll_calc_values() is always 21-bit, so the poll in hopping_hw_flow()
> never matches and every hop runs to the 1000 us timeout. The PLL does reach
> the requested rate and clk_change_rate() discards the error, so the cost is
> 1 ms of atomic polling plus a warning and a register dump on each rate
> change.
>
> Six MMPLL rate changes on an Amazon Fire HD 10 (2017) all time out with
> GENMASK(21, 0), MON reading the requested DDS with bit 21 set, and all pass
> with GENMASK(20, 0).
>
> mt8186, mt8192 and mt8195 share the constant but are correct, as their
> hoppable PLLs really are 22-bit. mt6795 is fixed in the next patch.
>
> Fixes: 45a5cbe05d1f ("clk: mediatek: mt8173: Add support for frequency hopping through FHCTL")
> Assisted-by: LLM
> Signed-off-by: Ryan Brue <ryanbrue.dev@xxxxxxxxx>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@xxxxxxxxxxxxx>