Re: [PATCH 3/5] arm64: dts: qcom: glymur: Add UFS nodes

From: Abel Vesa

Date: Mon Sep 14 2026 - 10:20:56 EST


On 26-09-11 22:17:07, Pradeep P V K wrote:
> Add UFS PHY and UFS host controller nodes for Glymur SoC.
>
> Signed-off-by: Pradeep P V K <pradeep.pragallapati@xxxxxxxxxxxxxxxx>

One nit below.

With Konrad's comments addressed, I think it looks good, so:

Reviewed-by: Abel Vesa <abel.vesa@xxxxxxxxxxxxxxxx>

> ---
> arch/arm64/boot/dts/qcom/glymur.dtsi | 114 ++++++++++++++++++++++++++++++++++-
> 1 file changed, 111 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
> index 624a9edd602c..7bbc804ed340 100644
> --- a/arch/arm64/boot/dts/qcom/glymur.dtsi
> +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
> @@ -812,9 +812,9 @@ gcc: clock-controller@100000 {
> <0>, /* QUSB4 1 PHY RX 1 */
> <0>, /* QUSB4 2 PHY RX 0 */
> <0>, /* QUSB4 2 PHY RX 1 */
> - <0>, /* UFS PHY RX Symbol 0 */
> - <0>, /* UFS PHY RX Symbol 1 */
> - <0>, /* UFS PHY TX Symbol 0 */
> + <&ufs_mem_phy 0>, /* UFS PHY RX Symbol 0 */
> + <&ufs_mem_phy 1>, /* UFS PHY RX Symbol 1 */
> + <&ufs_mem_phy 2>, /* UFS PHY TX Symbol 0 */
> <&usb_0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
> <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
> <&usb_2_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
> @@ -4103,6 +4103,114 @@ rng: rng@10c3000 {
> reg = <0x0 0x010c3000 0x0 0x1000>;
> };
>
> + ufs_mem_phy: phy@1d80000 {
> + compatible = "qcom,glymur-qmp-ufs-phy";
> + reg = <0x0 0x01d80000 0x0 0x2000>;
> +
> + clocks = <&rpmhcc RPMH_CXO_CLK>,
> + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
> + /* UFS and PCIE4 shares the same clkref on glymur */

On top of Konrad's comment, I'd drop the "on glymur" part entirely here.