Re: [PATCH 1/5] arm64: dts: qcom: nord: Add PCIe PHY and controller nodes

[Abel Vesa]

On 26-09-14 15:30:09, Shawn Guo wrote:
> On Mon, Sep 14, 2026 at 03:19:40PM +0800, Shawn Guo wrote:
> > From: Krishna Chaitanya Chundru <krishna.chundru@xxxxxxxxxxxxxxxx>
> > 
> > Nord has four PCIe controllers backed by a single quadfurcated Gen5
> > QMP PHY with four ports (A/B/C/D) and a common PCIe SMMU.  The ports
> > can be ganged into x16, x8+x8, x8+x4+x4 or x8+x4+x2+x2 topologies; the
> > topology in effect is selected by firmware through the TCSR link-config
> > mode register, which the PHY driver reads at probe time.  Describe the
> > x8+x4+x2+x2 topology, i.e. all four controllers usable, as that is the
> > configuration the boards ship with.
> > 
> > Add the controller and SMMU nodes to nord.dtsi, and the PHY node along
> > with the per-controller clocks, resets, GDSCs, interconnects, OPP tables
> > and TLMM pin states to nord-embedded.dtsi.  The four PCIe pipe clocks
> > also become available now, so hook them up as GCC parents in place of
> > the <0> placeholders.
> > 
> > The controllers and the PHY are left disabled here and enabled per
> > board.
> > 
> > Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@xxxxxxxxxxxxxxxx>
> > Signed-off-by: Shawn Guo <shengchao.guo@xxxxxxxxxxxxxxxx>

With your own comment addressed:

Reviewed-by: Abel Vesa <abel.vesa@xxxxxxxxxxxxxxxx>