Re: [PATCH RESEND v4 0/3] x86/apic: Add support for additional AMD EILVT registers

[Borislav Petkov]

On Thu, Sep 03, 2026 at 02:58:38PM +0530, Naveen N Rao (AMD) wrote:
> Add support for additional APIC EILVT registers being introduced in 
> future AMD processors:
> https://docs.amd.com/v/u/en-US/69205_1.00_AMD64_IBS_PUB)
> 
> This is a resend of v4, rebased on tip/master. Previous posting:
> http://lore.kernel.org/r/cover.1784785046.git.naveen@xxxxxxxxxx
> 
> Since then:
> - I have retained the macro name 'APIC_EILVT_NR_AMD_10H' since I felt it 
>   is accurate, and didn't hear a preference for anything else. Happy to 
>   change if needed (Ingo)
> - I have gone through Sashiko's findings on the previous versions, and 
>   none of those justified a change. Other than the pre-existing issues
>   reported by Sashiko, there have been 3 findings:

Except that someone should address the preexisting issues before we pile more
ontop:

https://sashiko.dev/#/patchset/cover.1788425679.git.naveen%40kernel.org

I see Ravi looks like the one who's been most busy here. CCed.

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette