Re: [PATCH v8 16/19] dmaengine: ti: k3-udma-v2: New driver for K3 BCDMA_V2

[Vignesh Raghavendra]

> Add support for BCDMA_V2.
> 
> The BCDMA_V2 is different than the existing BCDMA supported by the
> k3-udma driver.
> 
> The changes in BCDMA_V2 are:
> - Autopair: There is no longer a need for PSIL pair and AUTOPAIR bit
>   needs to set in the RT_CTL register.
> - Static channel mapping: Each channel is mapped to a single peripheral.
> - Direct IRQs: There is no INT-A and interrupt lines from DMA are
>   directly connected to GIC.
> - Remote side configuration handled by DMA. So no need to write to PEER
>   registers to START / STOP / PAUSE / TEARDOWN.
> - Unified Channel Space: Tx and Rx channels share a single register
>   space. Each channel index is specifically fixed in hardware as either
>   Tx or Rx in an interleaved manner.
> 
> Also, since a version member is introduced in the match_data, Add
> version v1 in match_data of SoCs using v1 DMA.
> 
> Signed-off-by: Sai Sree Kartheek Adivi <s-adivi@xxxxxx>
>
> diff --git a/drivers/dma/ti/Kconfig b/drivers/dma/ti/Kconfig
> index 712e45601545..40713bd1e8e9 100644
> --- a/drivers/dma/ti/Kconfig
> +++ b/drivers/dma/ti/Kconfig
> @@ -49,6 +49,18 @@ config TI_K3_UDMA
>  	  Enable support for the TI UDMA (Unified DMA) controller. This
>  	  DMA engine is used in AM65x and j721e.
>  
> +config TI_K3_UDMA_V2
> +	tristate "Texas Instruments K3 UDMA v2 support"
> +	depends on ARCH_K3
> +	select DMA_ENGINE
> +	select DMA_VIRTUAL_CHANNELS
> +	select TI_K3_UDMA_COMMON
> +	select TI_K3_RINGACC
> +	select TI_K3_PSIL
> +        help
> +	  Enable support for the TI UDMA (Unified DMA) v2 controller. This
> +	  DMA engine is used in AM62L.
> +
>  config TI_K3_UDMA_COMMON
>  	tristate
>  	default n
> @@ -63,7 +75,7 @@ config TI_K3_UDMA_GLUE_LAYER
>  
>  config TI_K3_PSIL
>         tristate
> -       default TI_K3_UDMA
> +       default TI_K3_UDMA || TI_K3_UDMA_V2
>  
>  config TI_DMA_CROSSBAR
>  	bool
> diff --git a/drivers/dma/ti/Makefile b/drivers/dma/ti/Makefile
> index 41bfba944dc6..296aa3421e71 100644
> --- a/drivers/dma/ti/Makefile
> +++ b/drivers/dma/ti/Makefile
> @@ -3,6 +3,7 @@ obj-$(CONFIG_TI_CPPI41) += cppi41.o
>  obj-$(CONFIG_TI_EDMA) += edma.o
>  obj-$(CONFIG_DMA_OMAP) += omap-dma.o
>  obj-$(CONFIG_TI_K3_UDMA) += k3-udma.o
> +obj-$(CONFIG_TI_K3_UDMA_V2) += k3-udma-v2.o
>  obj-$(CONFIG_TI_K3_UDMA_COMMON) += k3-udma-common.o
>  obj-$(CONFIG_TI_K3_UDMA_GLUE_LAYER) += k3-udma-glue.o
>  k3-psil-lib-objs := k3-psil.o \
> diff --git a/drivers/dma/ti/k3-udma-common.c b/drivers/dma/ti/k3-udma-common.c
> index 01b66e9f026b..f9dd6edf3eac 100644
> --- a/drivers/dma/ti/k3-udma-common.c
> +++ b/drivers/dma/ti/k3-udma-common.c
> @@ -171,8 +171,13 @@ bool udma_is_desc_really_done(struct udma_chan *uc, struct udma_desc *d)
>  	    uc->config.dir != DMA_MEM_TO_DEV || !(uc->config.tx_flags & DMA_PREP_INTERRUPT))
>  		return true;
>  
> -	peer_bcnt = udma_tchanrt_read(uc, UDMA_CHAN_RT_PEER_BCNT_REG);
> -	bcnt = udma_tchanrt_read(uc, UDMA_CHAN_RT_BCNT_REG);
> +	if (uc->ud->match_data->version == K3_UDMA_V1) {
> +		peer_bcnt = udma_tchanrt_read(uc, UDMA_CHAN_RT_PEER_BCNT_REG);
> +		bcnt = udma_tchanrt_read(uc, UDMA_CHAN_RT_BCNT_REG);
> +	} else {
> +		peer_bcnt = udma_chanrt_read(uc, UDMA_CHAN_RT_PERIPH_BCNT_REG);
> +		bcnt = udma_chanrt_read(uc, UDMA_CHAN_RT_BCNT_REG);
> +	}
>  
>  	/* Transfer is incomplete, store current residue and time stamp */
>  	if (peer_bcnt < bcnt) {
> @@ -319,6 +324,7 @@ udma_prep_slave_sg_tr(struct udma_chan *uc, struct scatterlist *sgl,
>  	size_t tr_size;
>  	int num_tr = 0;
>  	int tr_idx = 0;
> +	u32 extra_flags = 0;
>  	u64 asel;
>  
>  	/* estimate the number of TRs we will need */
> @@ -342,6 +348,16 @@ udma_prep_slave_sg_tr(struct udma_chan *uc, struct scatterlist *sgl,
>  	else
>  		asel = (u64)uc->config.asel << K3_ADDRESS_ASEL_SHIFT;
>  
> +	/*
> +	 * BCDMA V2 stalls and stops processing further TRs if a TR's ICNT0
> +	 * is not a multiple of 16 bytes. Setting EOP on every TR (not just
> +	 * the last one) avoids that stall condition. Intentional, not a bug.
> +	 */
> +	if (uc->ud->match_data->type == DMA_TYPE_BCDMA &&
> +	    uc->ud->match_data->version == K3_UDMA_V2 &&
> +	    dir == DMA_MEM_TO_DEV)
> +		extra_flags = CPPI5_TR_CSF_EOP;
> +
>  	tr_req = d->hwdesc[0].tr_req_base;
>  	for_each_sg(sgl, sgent, sglen, i) {
>  		dma_addr_t sg_addr = sg_dma_address(sgent);
> @@ -358,7 +374,7 @@ udma_prep_slave_sg_tr(struct udma_chan *uc, struct scatterlist *sgl,
>  
>  		cppi5_tr_init(&tr_req[tr_idx].flags, CPPI5_TR_TYPE1, false,
>  			      false, CPPI5_TR_EVENT_SIZE_COMPLETION, 0);
> -		cppi5_tr_csf_set(&tr_req[tr_idx].flags, CPPI5_TR_CSF_SUPR_EVT);
> +		cppi5_tr_csf_set(&tr_req[tr_idx].flags, CPPI5_TR_CSF_SUPR_EVT | extra_flags);
>  
>  		sg_addr |= asel;
>  		tr_req[tr_idx].addr = sg_addr;
> @@ -372,7 +388,7 @@ udma_prep_slave_sg_tr(struct udma_chan *uc, struct scatterlist *sgl,
>  				      false, false,
>  				      CPPI5_TR_EVENT_SIZE_COMPLETION, 0);
>  			cppi5_tr_csf_set(&tr_req[tr_idx].flags,
> -					 CPPI5_TR_CSF_SUPR_EVT);
> +					 CPPI5_TR_CSF_SUPR_EVT | extra_flags);
>  
>  			tr_req[tr_idx].addr = sg_addr + tr0_cnt1 * tr0_cnt0;
>  			tr_req[tr_idx].icnt0 = tr1_cnt0;
> @@ -593,7 +609,7 @@ int udma_configure_statictr(struct udma_chan *uc, struct udma_desc *d,
>  			    enum dma_slave_buswidth dev_width,
>  			    u16 elcnt)
>  {
> -	if (uc->config.ep_type != PSIL_EP_PDMA_XY)
> +	if (uc->config.ep_type != PSIL_EP_PDMA_XY && uc->config.ep_type != PSIL_EP_PDMA_XYMF)
>  		return 0;
>  
>  	/* Bus width translates to the element size (ES) */
> @@ -951,7 +967,8 @@ udma_prep_dma_cyclic_tr(struct udma_chan *uc, dma_addr_t buf_addr,
>  	 * As we are in cyclic mode, we do not know which period might be the
>  	 * last one, so set the flag for each period.
>  	 */
> -	if (uc->config.ep_type == PSIL_EP_PDMA_XY &&
> +	if ((uc->config.ep_type == PSIL_EP_PDMA_XY ||
> +	    uc->config.ep_type == PSIL_EP_PDMA_XYMF) &&
>  	    uc->ud->match_data->type == DMA_TYPE_BCDMA) {
>  		period_csf = CPPI5_TR_CSF_EOP;
>  	}
> @@ -2052,6 +2069,8 @@ int udma_get_tchan(struct udma_chan *uc)
>  		uc->tchan = NULL;
>  		return ret;
>  	}
> +	if (ud->match_data->version == K3_UDMA_V2)
> +		uc->chan = uc->tchan;
>  
>  	if (ud->tflow_cnt) {
>  		int tflow_id;
> @@ -2102,6 +2121,8 @@ int udma_get_rchan(struct udma_chan *uc)
>  		uc->rchan = NULL;
>  		return ret;
>  	}
> +	if (ud->match_data->version == K3_UDMA_V2)
> +		uc->chan = uc->rchan;
>  
>  	return 0;
>  }
> @@ -2383,9 +2404,16 @@ static int bcdma_setup_resources(struct udma_dev *ud)
>  	ud->tchan_map = devm_bitmap_zalloc(dev, ud->tchan_cnt, GFP_KERNEL);
>  	ud->tchans = devm_kcalloc(dev, ud->tchan_cnt, sizeof(*ud->tchans),
>  				  GFP_KERNEL);
> -	ud->rchan_map = devm_bitmap_zalloc(dev, ud->rchan_cnt, GFP_KERNEL);
> -	ud->rchans = devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rchans),
> -				  GFP_KERNEL);
> +	if (ud->match_data->version == K3_UDMA_V1) {
> +		ud->rchan_map = devm_bitmap_zalloc(dev, ud->rchan_cnt, GFP_KERNEL);
> +		ud->rchans = devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rchans),
> +					  GFP_KERNEL);
> +	} else {
> +		ud->rchan_map = ud->tchan_map;
> +		ud->rchans = ud->tchans;
> +		ud->chan_map = ud->tchan_map;
> +		ud->chans = ud->tchans;
> +	}
>  	/* BCDMA do not really have flows, but the driver expect it */
>  	ud->rflow_in_use = devm_kcalloc(dev, BITS_TO_LONGS(ud->rchan_cnt),
>  					sizeof(unsigned long),
> @@ -2480,11 +2508,18 @@ int k3_udma_setup_resources(struct udma_dev *ud)
>  	if (ret)
>  		return ret;
>  
> -	ch_count  = ud->bchan_cnt + ud->tchan_cnt + ud->rchan_cnt;
> -	if (ud->bchan_cnt)
> -		ch_count -= bitmap_weight(ud->bchan_map, ud->bchan_cnt);
> -	ch_count -= bitmap_weight(ud->tchan_map, ud->tchan_cnt);
> -	ch_count -= bitmap_weight(ud->rchan_map, ud->rchan_cnt);
> +	if (ud->match_data->version == K3_UDMA_V1) {
> +		ch_count  = ud->bchan_cnt + ud->tchan_cnt + ud->rchan_cnt;
> +		if (ud->bchan_cnt)
> +			ch_count -= bitmap_weight(ud->bchan_map, ud->bchan_cnt);
> +		ch_count -= bitmap_weight(ud->tchan_map, ud->tchan_cnt);
> +		ch_count -= bitmap_weight(ud->rchan_map, ud->rchan_cnt);
> +	} else {
> +		ch_count = ud->bchan_cnt + ud->tchan_cnt;
> +		if (ud->bchan_cnt)
> +			ch_count -= bitmap_weight(ud->bchan_map, ud->bchan_cnt);
> +		ch_count -= bitmap_weight(ud->tchan_map, ud->tchan_cnt);
> +	}
>  	if (!ch_count)
>  		return -ENODEV;
>  
> @@ -2506,15 +2541,25 @@ int k3_udma_setup_resources(struct udma_dev *ud)
>  						       ud->rflow_cnt));
>  		break;
>  	case DMA_TYPE_BCDMA:
> -		dev_info(dev,
> -			 "Channels: %d (bchan: %u, tchan: %u, rchan: %u)\n",
> -			 ch_count,
> -			 ud->bchan_cnt - bitmap_weight(ud->bchan_map,
> -						       ud->bchan_cnt),
> -			 ud->tchan_cnt - bitmap_weight(ud->tchan_map,
> -						       ud->tchan_cnt),
> -			 ud->rchan_cnt - bitmap_weight(ud->rchan_map,
> -						       ud->rchan_cnt));
> +		if (ud->match_data->version == K3_UDMA_V1) {
> +			dev_info(dev,
> +				 "Channels: %d (bchan: %u, tchan: %u, rchan: %u)\n",
> +				 ch_count,
> +				 ud->bchan_cnt - bitmap_weight(ud->bchan_map,
> +							       ud->bchan_cnt),
> +				 ud->tchan_cnt - bitmap_weight(ud->tchan_map,
> +							       ud->tchan_cnt),
> +				 ud->rchan_cnt - bitmap_weight(ud->rchan_map,
> +							       ud->rchan_cnt));
> +		} else {
> +			dev_info(dev,
> +				 "Channels: %d (bchan: %u, chan: %u)\n",
> +				 ch_count,
> +				 ud->bchan_cnt - bitmap_weight(ud->bchan_map,
> +							       ud->bchan_cnt),
> +				 ud->chan_cnt - bitmap_weight(ud->chan_map,
> +							      ud->chan_cnt));
> +		}
>  		break;
>  	case DMA_TYPE_PKTDMA:
>  		dev_info(dev,
> diff --git a/drivers/dma/ti/k3-udma-v2.c b/drivers/dma/ti/k3-udma-v2.c
> new file mode 100644
> index 000000000000..b9ce58d1934a
> --- /dev/null
> +++ b/drivers/dma/ti/k3-udma-v2.c
> @@ -0,0 +1,1319 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + *  Derived from K3 UDMA driver (k3-udma.c)
> + *  Copyright (C) 2024-2025 Texas Instruments Incorporated - http://www.ti.com
> + *  Author: Peter Ujfalusi <peter.ujfalusi@xxxxxx>
> + *  Author: Sai Sree Kartheek Adivi <s-adivi@xxxxxx>
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/dmaengine.h>
> +#include <linux/dma-mapping.h>
> +#include <linux/dmapool.h>
> +#include <linux/err.h>
> +#include <linux/init.h>
> +#include <linux/interrupt.h>
> +#include <linux/list.h>
> +#include <linux/platform_device.h>
> +#include <linux/slab.h>
> +#include <linux/spinlock.h>
> +#include <linux/sys_soc.h>
> +#include <linux/of.h>
> +#include <linux/of_dma.h>
> +#include <linux/of_irq.h>
> +#include <linux/workqueue.h>
> +#include <linux/completion.h>
> +#include <linux/iopoll.h>
> +#include <linux/soc/ti/k3-ringacc.h>
> +
> +#include "../virt-dma.h"
> +#include "k3-udma.h"
> +#include "k3-psil-priv.h"
> +
> +static const char * const v2_mmr_names[] = {
> +	[V2_MMR_GCFG] = "gcfg",
> +	[V2_MMR_BCHANRT] = "bchanrt",
> +	[V2_MMR_CHANRT] = "chanrt",
> +};
> +
> +static int udma_v2_check_chan_autopair_completion(struct udma_chan *uc)
> +{
> +	u32 val;
> +
> +	val = udma_chanrt_read(uc, UDMA_CHAN_RT_CTL_REG);
> +	if (val & UDMA_CHAN_RT_CTL_PAIR_TIMEOUT)
> +		return -ETIMEDOUT;
> +	else if (val & UDMA_CHAN_RT_CTL_PAIR_COMPLETE)
> +		return 1;
> +
> +	/* timeout didn't occur and also pairing didn't happen yet. */
> +	return 0;
> +}
> +
> +static bool udma_v2_is_chan_paused(struct udma_chan *uc)
> +{
> +	u32 val, pause_mask;
> +
> +	if (uc->config.dir == DMA_MEM_TO_MEM) {
> +		val = udma_chanrt_read(uc, UDMA_CHAN_RT_CTL_REG);
> +		pause_mask = UDMA_CHAN_RT_CTL_PAUSE;
> +	} else {
> +		val = udma_chanrt_read(uc, UDMA_CHAN_RT_PDMA_STATE_REG);
> +		pause_mask = UDMA_CHAN_RT_PDMA_STATE_PAUSE;
> +	}
> +
> +	if (val & pause_mask)
> +		return true;
> +
> +	return false;
> +}
> +
> +static void udma_v2_decrement_byte_counters(struct udma_chan *uc, u32 val)
> +{
> +	udma_chanrt_write(uc, UDMA_CHAN_RT_BCNT_REG, val);
> +	udma_chanrt_write(uc, UDMA_CHAN_RT_SBCNT_REG, val);
> +	if (uc->config.ep_type != PSIL_EP_NATIVE)
> +		udma_chanrt_write(uc, UDMA_CHAN_RT_PERIPH_BCNT_REG, val);
> +}
> +
> +static void udma_v2_reset_counters(struct udma_chan *uc)
> +{
> +	u32 val;
> +
> +	val = udma_chanrt_read(uc, UDMA_CHAN_RT_BCNT_REG);
> +	udma_chanrt_write(uc, UDMA_CHAN_RT_BCNT_REG, val);
> +
> +	val = udma_chanrt_read(uc, UDMA_CHAN_RT_SBCNT_REG);
> +	udma_chanrt_write(uc, UDMA_CHAN_RT_SBCNT_REG, val);
> +
> +	val = udma_chanrt_read(uc, UDMA_CHAN_RT_PCNT_REG);
> +	udma_chanrt_write(uc, UDMA_CHAN_RT_PCNT_REG, val);
> +
> +	if (!uc->bchan) {
> +		val = udma_chanrt_read(uc, UDMA_CHAN_RT_PERIPH_BCNT_REG);
> +		udma_chanrt_write(uc, UDMA_CHAN_RT_PERIPH_BCNT_REG, val);
> +	}
> +}
> +
> +static int udma_v2_reset_chan(struct udma_chan *uc, bool hard)
> +{
> +	udma_chanrt_write(uc, UDMA_CHAN_RT_CTL_REG, 0);
> +
> +	/* Reset all counters */
> +	udma_v2_reset_counters(uc);
> +
> +	/* Hard reset: re-initialize the channel to reset */
> +	if (hard) {
> +		struct udma_chan_config ucc_backup;
> +		int ret;
> +
> +		memcpy(&ucc_backup, &uc->config, sizeof(uc->config));
> +		uc->ud->ddev.device_free_chan_resources(&uc->vc.chan);
> +
> +		/* restore the channel configuration */
> +		memcpy(&uc->config, &ucc_backup, sizeof(uc->config));
> +		ret = uc->ud->ddev.device_alloc_chan_resources(&uc->vc.chan);
> +		if (ret)
> +			return ret;
> +
> +		/*
> +		 * Setting forced teardown after forced reset helps recovering
> +		 * the rchan.
> +		 */
> +		if (uc->config.dir == DMA_DEV_TO_MEM)
> +			udma_chanrt_update_bits(uc, UDMA_CHAN_RT_CTL_REG,
> +						UDMA_CHAN_RT_CTL_EN | UDMA_CHAN_RT_CTL_TDOWN |
> +						UDMA_CHAN_RT_CTL_FTDOWN,
> +						UDMA_CHAN_RT_CTL_EN | UDMA_CHAN_RT_CTL_TDOWN |
> +						UDMA_CHAN_RT_CTL_FTDOWN);
> +	}
> +	uc->state = UDMA_CHAN_IS_IDLE;
> +
> +	return 0;
> +}
> +
> +static int udma_v2_start(struct udma_chan *uc)
> +{
> +	struct virt_dma_desc *vd = vchan_next_desc(&uc->vc);
> +	struct udma_dev *ud = uc->ud;
> +	int status;
> +
> +	if (!vd) {
> +		uc->desc = NULL;
> +		return -ENOENT;
> +	}
> +
> +	list_del(&vd->node);
> +
> +	uc->desc = to_udma_desc(&vd->tx);
> +
> +	/* Channel is already running and does not need reconfiguration */
> +	if (udma_is_chan_running(uc) && !udma_chan_needs_reconfiguration(uc)) {
> +		udma_start_desc(uc);
> +		goto out;
> +	}
> +
> +	/* Make sure that we clear the teardown bit, if it is set */
> +	ud->reset_chan(uc, false);
> +
> +	/* Push descriptors before we start the channel */
> +	udma_start_desc(uc);
> +
> +	switch (uc->config.dir) {
> +	case DMA_DEV_TO_MEM:
> +		/* Config remote TR */
> +		if (uc->config.ep_type == PSIL_EP_PDMA_XY ||
> +		    uc->config.ep_type == PSIL_EP_PDMA_XYMF) {
> +			u32 val = PDMA_STATIC_TR_Y(uc->desc->static_tr.elcnt) |
> +				  PDMA_STATIC_TR_X(uc->desc->static_tr.elsize);
> +			const struct udma_match_data *match_data =
> +							uc->ud->match_data;
> +
> +			if (uc->config.enable_acc32)
> +				val |= PDMA_STATIC_TR_XY_ACC32;
> +			if (uc->config.enable_burst)
> +				val |= PDMA_STATIC_TR_XY_BURST;
> +
> +			udma_chanrt_write(uc,
> +					  UDMA_CHAN_RT_STATIC_TR_XY_REG,
> +					  val);
> +
> +			udma_chanrt_write(uc,
> +					  UDMA_CHAN_RT_STATIC_TR_Z_REG,
> +					  PDMA_STATIC_TR_Z(uc->desc->static_tr.bstcnt,
> +							   match_data->statictr_z_mask));
> +
> +			/* save the current staticTR configuration */
> +			memcpy(&uc->static_tr, &uc->desc->static_tr,
> +			       sizeof(uc->static_tr));
> +		}
> +
> +		if (uc->config.ep_type == PSIL_EP_PDMA_XYMF)
> +			udma_chanrt_write(uc, UDMA_CHAN_RT_FIFO_SEL_REG, uc->config.fifo_id);
> +
> +		udma_chanrt_write(uc, UDMA_CHAN_RT_CTL_REG,
> +				  UDMA_CHAN_RT_CTL_EN | UDMA_CHAN_RT_CTL_AUTOPAIR);
> +
> +		/* Poll for autopair completion */
> +		read_poll_timeout_atomic(udma_v2_check_chan_autopair_completion,
> +					 status, status != 0, 100, 500, false, uc);
> +
> +		if (status <= 0)
> +			return -ETIMEDOUT;
> +
> +		break;
> +	case DMA_MEM_TO_DEV:
> +		/* Config remote TR */
> +		if (uc->config.ep_type == PSIL_EP_PDMA_XY ||
> +		    uc->config.ep_type == PSIL_EP_PDMA_XYMF) {
> +			u32 val = PDMA_STATIC_TR_Y(uc->desc->static_tr.elcnt) |
> +				  PDMA_STATIC_TR_X(uc->desc->static_tr.elsize);
> +
> +			if (uc->config.enable_acc32)
> +				val |= PDMA_STATIC_TR_XY_ACC32;
> +			if (uc->config.enable_burst)
> +				val |= PDMA_STATIC_TR_XY_BURST;
> +
> +			udma_chanrt_write(uc,
> +					  UDMA_CHAN_RT_STATIC_TR_XY_REG,
> +					  val);
> +
> +			/* save the current staticTR configuration */
> +			memcpy(&uc->static_tr, &uc->desc->static_tr,
> +			       sizeof(uc->static_tr));
> +		}
> +
> +		if (uc->config.ep_type == PSIL_EP_PDMA_XYMF)
> +			udma_chanrt_write(uc, UDMA_CHAN_RT_FIFO_SEL_REG, uc->config.fifo_id);
> +
> +		udma_chanrt_write(uc, UDMA_CHAN_RT_CTL_REG,
> +				  UDMA_CHAN_RT_CTL_EN | UDMA_CHAN_RT_CTL_AUTOPAIR);
> +
> +		/* Poll for autopair completion */
> +		read_poll_timeout_atomic(udma_v2_check_chan_autopair_completion,
> +					 status, status != 0, 100, 500, false, uc);
> +
> +		if (status <= 0)
> +			return -ETIMEDOUT;
> +
> +		break;
> +	case DMA_MEM_TO_MEM:
> +		udma_bchanrt_write(uc, UDMA_CHAN_RT_CTL_REG,
> +				   UDMA_CHAN_RT_CTL_EN);
> +		udma_bchanrt_write(uc, UDMA_CHAN_RT_CTL_REG,
> +				   UDMA_CHAN_RT_CTL_EN);
> +
> +		break;
> +	default:
> +		return -EINVAL;
> +	}
> +
> +	uc->state = UDMA_CHAN_IS_ACTIVE;
> +out:
> +
> +	return 0;
> +}
> +
> +static int udma_v2_stop(struct udma_chan *uc)
> +{
> +	uc->state = UDMA_CHAN_IS_TERMINATING;
> +	reinit_completion(&uc->teardown_completed);
> +
> +	if (uc->config.dir == DMA_DEV_TO_MEM) {
> +		if (!uc->cyclic && !uc->desc)
> +			udma_push_to_ring(uc, -1);
> +	}
> +
> +	if (uc->config.dir != DMA_MEM_TO_MEM)
> +		udma_chanrt_write(uc, UDMA_CHAN_RT_PEER_REG(8), UDMA_CHAN_RT_PEER_REG8_FLUSH);
> +
> +	udma_chanrt_update_bits(uc, UDMA_CHAN_RT_CTL_REG,
> +				UDMA_CHAN_RT_CTL_EN | UDMA_CHAN_RT_CTL_TDOWN,
> +				UDMA_CHAN_RT_CTL_EN | UDMA_CHAN_RT_CTL_TDOWN);
> +
> +	return 0;
> +}
> +
> +static irqreturn_t udma_v2_udma_irq_handler(int irq, void *data)
> +{
> +	struct udma_chan *uc = data;
> +	struct udma_dev *ud = uc->ud;
> +	struct udma_desc *d;
> +
> +	switch (uc->config.dir) {
> +	case DMA_DEV_TO_MEM:
> +		k3_ringacc_ring_clear_irq(uc->rflow->r_ring);
> +		break;
> +	case DMA_MEM_TO_DEV:
> +	case DMA_MEM_TO_MEM:
> +		k3_ringacc_ring_clear_irq(uc->tchan->tc_ring);
> +		break;
> +	default:
> +		return -ENOENT;
> +	}
> +
> +	spin_lock(&uc->vc.lock);
> +	d = uc->desc;
> +	if (d) {
> +		d->tr_idx = (d->tr_idx + 1) % d->sglen;
> +
> +		if (uc->cyclic) {
> +			vchan_cyclic_callback(&d->vd);
> +		} else {
> +			/* TODO: figure out the real amount of data */
> +			ud->decrement_byte_counters(uc, d->residue);
> +			ud->start(uc);
> +			vchan_cookie_complete(&d->vd);
> +		}
> +	}
> +
> +	spin_unlock(&uc->vc.lock);
> +
> +	return IRQ_HANDLED;
> +}
> +
> +static irqreturn_t udma_v2_ring_irq_handler(int irq, void *data)
> +{
> +	struct udma_chan *uc = data;
> +	struct udma_dev *ud = uc->ud;
> +	struct udma_desc *d;
> +	dma_addr_t paddr = 0;
> +	u32 intr_status, reg;
> +
> +	switch (uc->config.dir) {
> +	case DMA_DEV_TO_MEM:
> +		intr_status =  k3_ringacc_ring_get_irq_status(uc->rflow->r_ring);
> +		break;
> +	case DMA_MEM_TO_DEV:
> +	case DMA_MEM_TO_MEM:
> +		intr_status =  k3_ringacc_ring_get_irq_status(uc->tchan->tc_ring);
> +		break;
> +	default:
> +		return IRQ_NONE;
> +	}
> +
> +	if (!intr_status)
> +		return IRQ_NONE;	/* Not this channel's interrupt */
> +
> +	reg = udma_chanrt_read(uc, UDMA_CHAN_RT_CTL_REG);

Move this read inside the if() condition below

> +
> +	if (intr_status & K3_RINGACC_RT_INT_STATUS_TR) {
> +		/* check teardown status */
> +		if ((reg & UDMA_CHAN_RT_CTL_TDOWN) && !(reg & UDMA_CHAN_RT_CTL_EN))
> +			complete_all(&uc->teardown_completed);
> +		udma_v2_udma_irq_handler(irq, data);
> +
> +		if (!(intr_status & K3_RINGACC_RT_INT_STATUS_COMPLETE))
> +			return IRQ_HANDLED;
> +	}
> +
> +	if (udma_pop_from_ring(uc, &paddr) || !paddr)
> +		return IRQ_NONE;
> +
> +	spin_lock(&uc->vc.lock);
> +
> +	/* Teardown completion message */
> +	if (cppi5_desc_is_tdcm(paddr)) {
> +		complete_all(&uc->teardown_completed);
> +
> +		if (uc->terminated_desc) {
> +			udma_desc_free(&uc->terminated_desc->vd);
> +			uc->terminated_desc = NULL;
> +		}
> +
> +		if (!uc->desc)
> +			ud->start(uc);
> +
> +		goto out;
> +	}
> +
> +	d = udma_udma_desc_from_paddr(uc, paddr);
> +
> +	if (d) {
> +		dma_addr_t desc_paddr = udma_curr_cppi5_desc_paddr(d,
> +								   d->desc_idx);
> +		if (desc_paddr != paddr) {
> +			dev_err(uc->ud->dev, "not matching descriptors!\n");
> +			goto out;
> +		}
> +
> +		if (d == uc->desc) {
> +			/* active descriptor */
> +			if (uc->cyclic) {
> +				udma_cyclic_packet_elapsed(uc);
> +				vchan_cyclic_callback(&d->vd);
> +			} else {
> +				if (udma_is_desc_really_done(uc, d)) {
> +					ud->decrement_byte_counters(uc, d->residue);
> +					ud->start(uc);
> +					vchan_cookie_complete(&d->vd);
> +				} else {
> +					schedule_delayed_work(&uc->tx_drain.work,
> +							      0);
> +				}
> +			}
> +		} else {
> +			/*
> +			 * terminated descriptor, mark the descriptor as
> +			 * completed to update the channel's cookie marker
> +			 */
> +			dma_cookie_complete(&d->vd.tx);
> +		}
> +	}
> +out:
> +	spin_unlock(&uc->vc.lock);
> +
> +	return IRQ_HANDLED;
> +}
> +
> +static int bcdma_v2_get_bchan(struct udma_chan *uc)
> +{
> +	struct udma_dev *ud = uc->ud;
> +	enum udma_tp_level tpl;
> +	int ret;
> +
> +	if (uc->bchan) {
> +		dev_dbg(ud->dev, "chan%d: already have bchan%d allocated\n",
> +			uc->id, uc->bchan->id);
> +		return 0;
> +	}
> +
> +	/*
> +	 * Use normal channels for peripherals, and highest TPL channel for
> +	 * mem2mem
> +	 */
> +	if (uc->config.tr_trigger_type)
> +		tpl = 0;
> +	else
> +		tpl = ud->bchan_tpl.levels - 1;
> +
> +	/*
> +	 * UDMA V2 uses a static 1:1 mapping between the virtual channel index
> +	 * (uc->id) and the hardware bchan/tchan/rchan index -- unlike V1, which
> +	 * dynamically allocates from a shared pool. Passing uc->id directly to
> +	 * __udma_reserve_*() is intentional, not a bug.
> +	 */
> +	uc->bchan = __udma_reserve_bchan(ud, tpl, uc->id);
> +	if (IS_ERR(uc->bchan)) {
> +		ret = PTR_ERR(uc->bchan);
> +		uc->bchan = NULL;
> +		return ret;
> +	}
> +	uc->chan = uc->bchan;
> +	uc->tchan = uc->bchan;
> +
> +	return 0;
> +}
> +
> +static int bcdma_v2_alloc_bchan_resources(struct udma_chan *uc)
> +{
> +	struct k3_ring_cfg ring_cfg;
> +	struct udma_dev *ud = uc->ud;
> +	int ret;
> +
> +	ret = bcdma_v2_get_bchan(uc);
> +	if (ret)
> +		return ret;
> +
> +	ret = k3_ringacc_request_rings_pair(ud->ringacc, ud->match_data->chan_cnt + uc->id, -1,
> +					    &uc->bchan->t_ring,
> +					    &uc->bchan->tc_ring);
> +	if (ret) {
> +		ret = -EBUSY;
> +		goto err_ring;
> +	}
> +
> +	memset(&ring_cfg, 0, sizeof(ring_cfg));
> +	ring_cfg.size = K3_UDMA_DEFAULT_RING_SIZE;
> +	ring_cfg.elm_size = K3_RINGACC_RING_ELSIZE_8;
> +	ring_cfg.mode = K3_RINGACC_RING_MODE_RING;
> +
> +	k3_configure_chan_coherency(&uc->vc.chan, ud->asel);
> +	ring_cfg.asel = ud->asel;
> +	ring_cfg.dma_dev = dmaengine_get_dma_device(&uc->vc.chan);
> +
> +	ret = k3_ringacc_ring_cfg(uc->bchan->t_ring, &ring_cfg);
> +	if (ret)
> +		goto err_ringcfg;
> +
> +	return 0;
> +
> +err_ringcfg:
> +	k3_ringacc_ring_free(uc->bchan->tc_ring);
> +	uc->bchan->tc_ring = NULL;
> +	k3_ringacc_ring_free(uc->bchan->t_ring);
> +	uc->bchan->t_ring = NULL;
> +	k3_configure_chan_coherency(&uc->vc.chan, 0);
> +err_ring:
> +	bcdma_put_bchan(uc);
> +
> +	return ret;
> +}
> +
> +static int udma_v2_alloc_tx_resources(struct udma_chan *uc)
> +{
> +	struct k3_ring_cfg ring_cfg;
> +	struct udma_dev *ud = uc->ud;
> +	struct udma_tchan *tchan;
> +	int ring_idx, ret;
> +
> +	ret = udma_get_tchan(uc);
> +	if (ret)
> +		return ret;
> +
> +	tchan = uc->tchan;
> +	if (tchan->tflow_id >= 0)
> +		ring_idx = tchan->tflow_id;
> +	else
> +		ring_idx = tchan->id;
> +
> +	ret = k3_ringacc_request_rings_pair(ud->ringacc, ring_idx, -1,
> +					    &tchan->t_ring,
> +					    &tchan->tc_ring);
> +	if (ret) {
> +		ret = -EBUSY;
> +		goto err_ring;
> +	}
> +
> +	memset(&ring_cfg, 0, sizeof(ring_cfg));
> +	ring_cfg.size = K3_UDMA_DEFAULT_RING_SIZE;
> +	ring_cfg.elm_size = K3_RINGACC_RING_ELSIZE_8;
> +	ring_cfg.mode = K3_RINGACC_RING_MODE_RING;
> +
> +	k3_configure_chan_coherency(&uc->vc.chan, uc->config.asel);
> +	ring_cfg.asel = uc->config.asel;
> +	ring_cfg.dma_dev = dmaengine_get_dma_device(&uc->vc.chan);
> +
> +	ret = k3_ringacc_ring_cfg(tchan->t_ring, &ring_cfg);
> +	ret |= k3_ringacc_ring_cfg(tchan->tc_ring, &ring_cfg);
> +
> +	if (ret)
> +		goto err_ringcfg;
> +
> +	return 0;
> +
> +err_ringcfg:
> +	k3_ringacc_ring_free(uc->tchan->tc_ring);
> +	uc->tchan->tc_ring = NULL;
> +	k3_ringacc_ring_free(uc->tchan->t_ring);
> +	uc->tchan->t_ring = NULL;
> +err_ring:
> +	udma_put_tchan(uc);
> +
> +	return ret;
> +}
> +
> +static int udma_v2_alloc_rx_resources(struct udma_chan *uc)
> +{
> +	struct udma_dev *ud = uc->ud;
> +	struct k3_ring_cfg ring_cfg;
> +	struct udma_rflow *rflow;
> +	int fd_ring_id;
> +	int ret;
> +
> +	ret = udma_get_rchan(uc);
> +	if (ret)
> +		return ret;
> +
> +	/* For MEM_TO_MEM we don't need rflow or rings */
> +	if (uc->config.dir == DMA_MEM_TO_MEM)
> +		return 0;
> +
> +	if (uc->config.default_flow_id >= 0)
> +		ret = udma_get_rflow(uc, uc->config.default_flow_id);
> +	else
> +		ret = udma_get_rflow(uc, uc->rchan->id);
> +
> +	if (ret) {
> +		ret = -EBUSY;
> +		goto err_rflow;
> +	}
> +
> +	rflow = uc->rflow;
> +	if (ud->tflow_cnt)
> +		fd_ring_id = ud->tflow_cnt + rflow->id;
> +	else
> +		fd_ring_id = uc->rchan->id;
> +	ret = k3_ringacc_request_rings_pair(ud->ringacc, fd_ring_id, -1,
> +					    &rflow->fd_ring, &rflow->r_ring);
> +	if (ret) {
> +		ret = -EBUSY;
> +		goto err_ring;
> +	}
> +
> +	memset(&ring_cfg, 0, sizeof(ring_cfg));
> +
> +	ring_cfg.elm_size = K3_RINGACC_RING_ELSIZE_8;
> +	ring_cfg.size = K3_UDMA_DEFAULT_RING_SIZE;
> +	ring_cfg.mode = K3_RINGACC_RING_MODE_RING;
> +
> +	k3_configure_chan_coherency(&uc->vc.chan, uc->config.asel);
> +	ring_cfg.asel = uc->config.asel;
> +	ring_cfg.dma_dev = dmaengine_get_dma_device(&uc->vc.chan);
> +
> +	ret = k3_ringacc_ring_cfg(rflow->fd_ring, &ring_cfg);
> +
> +	ring_cfg.size = K3_UDMA_DEFAULT_RING_SIZE;
> +	ret |= k3_ringacc_ring_cfg(rflow->r_ring, &ring_cfg);
> +
> +	if (ret)
> +		goto err_ringcfg;
> +
> +	return 0;
> +
> +err_ringcfg:
> +	k3_ringacc_ring_free(rflow->r_ring);
> +	rflow->r_ring = NULL;
> +	k3_ringacc_ring_free(rflow->fd_ring);
> +	rflow->fd_ring = NULL;
> +err_ring:
> +	udma_put_rflow(uc);
> +err_rflow:
> +	udma_put_rchan(uc);
> +
> +	return ret;
> +}
> +
> +static int bcdma_v2_alloc_chan_resources(struct dma_chan *chan)
> +{
> +	struct udma_chan *uc = to_udma_chan(chan);
> +	struct udma_dev *ud = to_udma_dev(chan->device);
> +	struct platform_device *pdev = to_platform_device(ud->dev);
> +	char irq_name[10];
> +	u32 irq_ring_idx;
> +	int ret;
> +
> +	/* Only TR mode is supported */
> +	uc->config.pkt_mode = false;
> +
> +	/*
> +	 * Make sure that the completion is in a known state:
> +	 * No teardown, the channel is idle
> +	 */
> +	reinit_completion(&uc->teardown_completed);
> +	complete_all(&uc->teardown_completed);
> +	uc->state = UDMA_CHAN_IS_IDLE;
> +
> +	switch (uc->config.dir) {
> +	case DMA_MEM_TO_MEM:
> +		/* Non synchronized - mem to mem type of transfer */
> +		dev_dbg(uc->ud->dev, "%s: chan%d as MEM-to-MEM\n", __func__,
> +			uc->id);
> +
> +		ret = bcdma_v2_alloc_bchan_resources(uc);
> +		if (ret)
> +			return ret;
> +
> +		irq_ring_idx = ud->match_data->chan_cnt + uc->id;
> +		break;
> +	case DMA_MEM_TO_DEV:
> +		/* Slave transfer synchronized - mem to dev (TX) transfer */
> +		dev_dbg(uc->ud->dev, "%s: chan%d as MEM-to-DEV\n", __func__,
> +			uc->id);
> +
> +		ret = udma_v2_alloc_tx_resources(uc);
> +		if (ret) {
> +			uc->config.remote_thread_id = -1;
> +			return ret;
> +		}
> +
> +		uc->config.src_thread = ud->psil_base + uc->tchan->id;
> +		uc->config.dst_thread = uc->config.remote_thread_id;
> +		uc->config.dst_thread |= K3_PSIL_DST_THREAD_ID_OFFSET;
> +
> +		irq_ring_idx = uc->tchan->id;
> +
> +		break;
> +	case DMA_DEV_TO_MEM:
> +		/* Slave transfer synchronized - dev to mem (RX) transfer */
> +		dev_dbg(uc->ud->dev, "%s: chan%d as DEV-to-MEM\n", __func__,
> +			uc->id);
> +
> +		ret = udma_v2_alloc_rx_resources(uc);
> +		if (ret) {
> +			uc->config.remote_thread_id = -1;
> +			return ret;
> +		}
> +
> +		uc->config.src_thread = uc->config.remote_thread_id;
> +		uc->config.dst_thread = (ud->psil_base + uc->rchan->id) |
> +					K3_PSIL_DST_THREAD_ID_OFFSET;
> +
> +		irq_ring_idx = uc->rchan->id;
> +
> +		break;
> +	default:
> +		/* Can not happen */
> +		dev_err(uc->ud->dev, "%s: chan%d invalid direction (%u)\n",
> +			__func__, uc->id, uc->config.dir);
> +		return -EINVAL;
> +	}
> +
> +	/* check if the channel configuration was successful */
> +	if (ret)
> +		goto err_res_free;
> +
> +	if (udma_is_chan_running(uc)) {
> +		dev_warn(ud->dev, "chan%d: is running!\n", uc->id);
> +		ud->reset_chan(uc, false);
> +		if (udma_is_chan_running(uc)) {
> +			dev_err(ud->dev, "chan%d: won't stop!\n", uc->id);
> +			ret = -EBUSY;
> +			goto err_res_free;
> +		}
> +	}
> +
> +	uc->dma_dev = dmaengine_get_dma_device(chan);
> +	if (uc->config.dir == DMA_MEM_TO_MEM  && !uc->config.tr_trigger_type) {
> +		uc->config.hdesc_size =
> +			cppi5_trdesc_calc_size(sizeof(struct cppi5_tr_type15_t), 2);
> +
> +		uc->hdesc_pool = dma_pool_create(uc->name, ud->ddev.dev,
> +						 uc->config.hdesc_size,
> +						 ud->desc_align,
> +						 0);
> +		if (!uc->hdesc_pool) {
> +			dev_err(ud->ddev.dev,
> +				"Descriptor pool allocation failed\n");
> +			uc->use_dma_pool = false;
> +			ret = -ENOMEM;
> +			goto err_res_free;
> +		}
> +
> +		uc->use_dma_pool = true;
> +	} else if (uc->config.dir != DMA_MEM_TO_MEM) {
> +		uc->psil_paired = true;
> +	}
> +
> +	INIT_DELAYED_WORK(&uc->tx_drain.work, udma_check_tx_completion);
> +
> +	snprintf(irq_name, sizeof(irq_name), "chan%u", irq_ring_idx);
> +	uc->irq_num_ring = platform_get_irq_byname(pdev, irq_name);
> +	if (uc->irq_num_ring < 0) {
> +		ret = uc->irq_num_ring;
> +		goto err_res_free;
> +	}
> +
> +	ret = request_irq(uc->irq_num_ring, udma_v2_ring_irq_handler,
> +			  IRQF_SHARED | IRQF_TRIGGER_HIGH, uc->name, uc);
> +	if (ret) {
> +		dev_err(ud->dev, "chan%d: ring irq request failed\n", uc->id);
> +		goto err_irq_free;
> +	}
> +
> +	udma_reset_rings(uc);
> +
> +	return 0;
> +
> +err_irq_free:
> +	uc->irq_num_ring = 0;
> +	uc->irq_num_udma = 0;
> +err_res_free:
> +	bcdma_free_bchan_resources(uc);
> +	udma_free_tx_resources(uc);
> +	udma_free_rx_resources(uc);
> +
> +	udma_reset_uchan(uc);
> +
> +	if (uc->use_dma_pool) {
> +		dma_pool_destroy(uc->hdesc_pool);
> +		uc->use_dma_pool = false;
> +	}
> +
> +	return ret;
> +}
> +
> +static enum dma_status udma_v2_tx_status(struct dma_chan *chan,
> +					 dma_cookie_t cookie,
> +					 struct dma_tx_state *txstate)
> +{
> +	struct udma_chan *uc = to_udma_chan(chan);
> +	enum dma_status ret;
> +	unsigned long flags;
> +
> +	spin_lock_irqsave(&uc->vc.lock, flags);
> +
> +	ret = dma_cookie_status(chan, cookie, txstate);
> +
> +	if (!udma_is_chan_running(uc))
> +		ret = DMA_COMPLETE;
> +
> +	if (ret == DMA_IN_PROGRESS && udma_v2_is_chan_paused(uc))
> +		ret = DMA_PAUSED;
> +
> +	if (ret == DMA_COMPLETE || !txstate)
> +		goto out;
> +
> +	if (uc->desc && uc->desc->vd.tx.cookie == cookie) {
> +		u32 peer_bcnt = 0;
> +		u32 bcnt = 0;
> +		u32 residue = uc->desc->residue;
> +		u32 delay = 0;
> +
> +		if (uc->desc->dir == DMA_MEM_TO_DEV) {
> +			bcnt = udma_chanrt_read(uc, UDMA_CHAN_RT_SBCNT_REG);
> +
> +			if (uc->config.ep_type != PSIL_EP_NATIVE) {
> +				peer_bcnt = udma_chanrt_read(uc, UDMA_CHAN_RT_PERIPH_BCNT_REG);
> +
> +				if (bcnt > peer_bcnt)
> +					delay = bcnt - peer_bcnt;
> +			}
> +		} else if (uc->desc->dir == DMA_DEV_TO_MEM) {
> +			bcnt = udma_chanrt_read(uc, UDMA_CHAN_RT_BCNT_REG);
> +
> +			if (uc->config.ep_type != PSIL_EP_NATIVE) {
> +				peer_bcnt = udma_chanrt_read(uc, UDMA_CHAN_RT_PERIPH_BCNT_REG);
> +
> +				if (peer_bcnt > bcnt)
> +					delay = peer_bcnt - bcnt;
> +			}
> +		} else {
> +			bcnt = udma_chanrt_read(uc, UDMA_CHAN_RT_BCNT_REG);
> +		}
> +
> +		if (bcnt && !(bcnt % uc->desc->residue))
> +			residue = 0;
> +		else
> +			residue -= bcnt % uc->desc->residue;
> +
> +		if (!residue && (uc->config.dir == DMA_DEV_TO_MEM || !delay)) {
> +			ret = DMA_COMPLETE;
> +			delay = 0;
> +		}
> +
> +		dma_set_residue(txstate, residue);
> +		dma_set_in_flight_bytes(txstate, delay);
> +
> +	} else {
> +		ret = DMA_COMPLETE;
> +	}
> +
> +out:
> +	spin_unlock_irqrestore(&uc->vc.lock, flags);
> +	return ret;
> +}
> +
> +static int udma_v2_pause(struct dma_chan *chan)
> +{
> +	struct udma_chan *uc = to_udma_chan(chan);
> +	unsigned long flags;
> +
> +	/* pause the channel */
> +	spin_lock_irqsave(&uc->vc.lock, flags);
> +	udma_chanrt_update_bits(uc, UDMA_CHAN_RT_CTL_REG,
> +				UDMA_CHAN_RT_CTL_PAUSE, UDMA_CHAN_RT_CTL_PAUSE);
> +	spin_unlock_irqrestore(&uc->vc.lock, flags);
> +
> +	return 0;
> +}
> +
> +static int udma_v2_resume(struct dma_chan *chan)
> +{
> +	struct udma_chan *uc = to_udma_chan(chan);
> +	unsigned long flags;
> +
> +	/* resume the channel */
> +	spin_lock_irqsave(&uc->vc.lock, flags);
> +	udma_chanrt_update_bits(uc, UDMA_CHAN_RT_CTL_REG,
> +				UDMA_CHAN_RT_CTL_PAUSE, 0);
> +	spin_unlock_irqrestore(&uc->vc.lock, flags);
> +
> +	return 0;
> +}
> +
> +static struct platform_driver bcdma_v2_driver;
> +
> +static bool udma_v2_dma_filter_fn(struct dma_chan *chan, void *param)
> +{
> +	struct udma_v2_filter_param *filter_param;
> +	struct psil_endpoint_config *ep_config;
> +	struct udma_chan_config *ucc;
> +	struct udma_chan *uc;
> +	struct udma_dev *ud;
> +
> +	if (chan->device->dev->driver != &bcdma_v2_driver.driver)
> +		return false;
> +
> +	uc = to_udma_chan(chan);
> +	ucc = &uc->config;
> +	ud = uc->ud;
> +	filter_param = param;
> +
> +	if (filter_param->asel > 15) {
> +		dev_err(ud->dev, "Invalid channel asel: %u\n",
> +			filter_param->asel);
> +		return false;
> +	}
> +
> +	ucc->asel = filter_param->asel;
> +	ucc->tr_trigger_type = filter_param->tr_trigger_type;
> +
> +	if (ucc->tr_trigger_type) {
> +		ucc->dir = DMA_MEM_TO_MEM;
> +		goto triggered_bchan;
> +	} else {
> +		u32 thread_id;
> +		bool dev_to_mem;
> +
> +		ep_config = psil_get_ep_config_by_id(filter_param->channel_id,
> +						      (ud->match_data->type == DMA_TYPE_PKTDMA),
> +						      &thread_id, &dev_to_mem);
> +		if (IS_ERR(ep_config)) {
> +			dev_err(ud->dev, "No config for channel %u\n",
> +				filter_param->channel_id);
> +			ucc->atype = 0;
> +			ucc->asel = 0;
> +			return false;
> +		}
> +		ucc->remote_thread_id = thread_id;
> +		ucc->dir = dev_to_mem ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV;
> +	}
> +	if (IS_ERR(ep_config)) {
> +		dev_err(ud->dev, "No configuration for psi-l thread 0x%04x\n",
> +			ucc->remote_thread_id);
> +		ucc->dir = DMA_MEM_TO_MEM;
> +		ucc->remote_thread_id = -1;
> +		ucc->atype = 0;
> +		ucc->asel = 0;
> +		return false;
> +	}
> +
> +	ucc->pkt_mode = ep_config->pkt_mode;
> +	ucc->channel_tpl = ep_config->channel_tpl;
> +	ucc->notdpkt = ep_config->notdpkt;
> +	ucc->ep_type = ep_config->ep_type;
> +	ucc->fifo_id = ep_config->fifo_id;
> +
> +	if (ud->match_data->version == K3_UDMA_V2 &&
> +	    ep_config->mapped_channel_id >= 0) {
> +		ucc->mapped_channel_id = ep_config->mapped_channel_id;
> +		ucc->default_flow_id = ep_config->default_flow_id;
> +	} else {
> +		ucc->mapped_channel_id = -1;
> +		ucc->default_flow_id = -1;
> +	}
> +
> +	ucc->needs_epib = ep_config->needs_epib;
> +	ucc->psd_size = ep_config->psd_size;
> +	ucc->metadata_size =
> +		(ucc->needs_epib ? CPPI5_INFO0_HDESC_EPIB_SIZE : 0) +
> +		ucc->psd_size;
> +
> +	if (ucc->ep_type != PSIL_EP_NATIVE) {
> +		const struct udma_match_data *match_data = ud->match_data;
> +
> +		if ((match_data->flags & UDMA_FLAG_PDMA_ACC32) && ep_config->pdma_acc32)
> +			ucc->enable_acc32 = true;
> +		else
> +			ucc->enable_acc32 = false;
> +
> +		if ((match_data->flags & UDMA_FLAG_PDMA_BURST) && ep_config->pdma_burst)
> +			ucc->enable_burst = true;
> +		else
> +			ucc->enable_burst = false;
> +	}
> +	if (ucc->pkt_mode)
> +		ucc->hdesc_size = ALIGN(sizeof(struct cppi5_host_desc_t) +
> +				 ucc->metadata_size, ud->desc_align);
> +
> +	dev_dbg(ud->dev, "chan%d: Remote thread: 0x%04x (%s)\n", uc->id,
> +		ucc->remote_thread_id, dmaengine_get_direction_text(ucc->dir));
> +
> +	return true;
> +
> +triggered_bchan:
> +	dev_dbg(ud->dev, "chan%d: triggered channel (type: %u)\n", uc->id,
> +		ucc->tr_trigger_type);
> +
> +	return true;
> +}
> +
> +static struct dma_chan *udma_v2_of_xlate(struct of_phandle_args *dma_spec,
> +					 struct of_dma *ofdma)
> +{
> +	struct udma_dev *ud = ofdma->of_dma_data;
> +	dma_cap_mask_t mask = ud->ddev.cap_mask;
> +	struct udma_v2_filter_param filter_param;
> +	struct dma_chan *chan;
> +
> +	if (ud->match_data->type == DMA_TYPE_BCDMA) {
> +		if (dma_spec->args_count != 4)
> +			return NULL;
> +
> +		filter_param.tr_trigger_type = dma_spec->args[0];
> +		filter_param.trigger_param = dma_spec->args[1];
> +		filter_param.channel_id = dma_spec->args[2];
> +		filter_param.asel = dma_spec->args[3];
> +	} else {
> +		if (dma_spec->args_count != 1 && dma_spec->args_count != 2)
> +			return NULL;
> +
> +		filter_param.channel_id = dma_spec->args[0];
> +		filter_param.tr_trigger_type = 0;
> +		if (dma_spec->args_count == 2)
> +			filter_param.asel = dma_spec->args[1];
> +		else
> +			filter_param.asel = 0;
> +	}
> +
> +	chan = __dma_request_channel(&mask, udma_v2_dma_filter_fn, &filter_param,
> +				     ofdma->of_node);
> +	if (!chan) {
> +		dev_err(ud->dev, "get channel fail in %s.\n", __func__);
> +		return ERR_PTR(-EINVAL);
> +	}
> +
> +	return chan;
> +}
> +
> +static struct udma_match_data bcdma_v2_am62l_data = {
> +	.type = DMA_TYPE_BCDMA,
> +	.version = K3_UDMA_V2,
> +	.psil_base = 0x2000, /* for tchan and rchan, not applicable to bchan */
> +	.enable_memcpy_support = true, /* Supported via bchan */
> +	.flags = UDMA_FLAGS_J7_CLASS,
> +	.statictr_z_mask = GENMASK(23, 0),
> +	.burst_size = {
> +		TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_64_BYTES, /* Normal Channels */
> +		0, /* No H Channels */
> +		0, /* No UH Channels */
> +	},
> +	.bchan_cnt = 16,
> +	.chan_cnt = 128,
> +	.tchan_cnt = 128,
> +	.rchan_cnt = 128,
> +};
> +
> +static const struct of_device_id udma_of_match[] = {
> +	{
> +		.compatible = "ti,am62l-dmss-bcdma",
> +		.data = &bcdma_v2_am62l_data,
> +	},
> +	{ /* Sentinel */ },
> +};
> +
> +static const struct soc_device_attribute k3_soc_devices[] = {
> +	{ .family = "AM62LX", },
> +	{ /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, udma_of_match);
> +
> +static int udma_v2_get_mmrs(struct platform_device *pdev, struct udma_dev *ud)
> +{
> +	int i;
> +
> +	ud->mmrs[V2_MMR_GCFG] = devm_platform_ioremap_resource_byname(pdev,
> +								      v2_mmr_names[V2_MMR_GCFG]);
> +	if (IS_ERR(ud->mmrs[V2_MMR_GCFG]))
> +		return PTR_ERR(ud->mmrs[V2_MMR_GCFG]);
> +
> +	ud->bchan_cnt = ud->match_data->bchan_cnt;
> +	/* There are no tchan and rchan in BCDMA_V2.
> +	 * Duplicate chan as tchan and rchan to keep the common code
> +	 * in k3-udma-common.c functional for BCDMA_V2.
> +	 */
> +	ud->chan_cnt = ud->match_data->chan_cnt;
> +	ud->tchan_cnt = ud->match_data->chan_cnt;
> +	ud->rchan_cnt = ud->match_data->chan_cnt;
> +	ud->rflow_cnt = ud->chan_cnt;
> +
> +	for (i = 1; i < V2_MMR_LAST; i++) {
> +		if (i == V2_MMR_BCHANRT && ud->bchan_cnt == 0)
> +			continue;
> +		if (i == V2_MMR_CHANRT && ud->chan_cnt == 0)
> +			continue;
> +
> +		ud->mmrs[i] = devm_platform_ioremap_resource_byname(pdev, v2_mmr_names[i]);
> +		if (IS_ERR(ud->mmrs[i]))
> +			return PTR_ERR(ud->mmrs[i]);
> +	}
> +
> +	return 0;
> +}
> +
> +static int udma_v2_probe(struct platform_device *pdev)
> +{
> +	const struct soc_device_attribute *soc;
> +	struct device *dev = &pdev->dev;
> +	const struct of_device_id *match;
> +	struct udma_dev *ud;
> +	int ch_count, i, ret;
> +
> +	ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(48));
> +	if (ret)
> +		dev_err(dev, "failed to set dma mask stuff\n");
> +
> +	ud = devm_kzalloc(dev, sizeof(*ud), GFP_KERNEL);
> +	if (!ud)
> +		return -ENOMEM;
> +
> +	match = of_match_node(udma_of_match, dev->of_node);
> +	if (!match) {
> +		dev_err(dev, "No compatible match found\n");
> +		return -ENODEV;
> +	}
> +	ud->match_data = match->data;
> +
> +	ud->soc_data = ud->match_data->soc_data;
> +	if (!ud->soc_data) {
> +		soc = soc_device_match(k3_soc_devices);
> +		if (!soc) {
> +			dev_err(dev, "No compatible SoC found\n");
> +			return -ENODEV;
> +		}
> +		ud->soc_data = soc->data;
> +	}

> +	// Setup function pointers

This is obvious, please drop the comment

-- 
Vignesh