[PATCH 07/30] crypto: sa2ul - consolidate encryption offset definitions
From: Manorit Chawdhry
Date: Tue Sep 15 2026 - 06:09:08 EST
Move all SA2UL encryption offset macro definitions to a single
location for better maintainability. No functional change.
Assisted-by: Sisyphus:claude-sonnet-4-6
Signed-off-by: Manorit Chawdhry <m-chawdhry@xxxxxx>
---
drivers/crypto/sa2ul.c | 44 ++++++++++++++++++++++++++++----------------
drivers/crypto/sa2ul.h | 13 -------------
2 files changed, 28 insertions(+), 29 deletions(-)
diff --git a/drivers/crypto/sa2ul.c b/drivers/crypto/sa2ul.c
index 09cefd766c95..cde08686f27a 100644
--- a/drivers/crypto/sa2ul.c
+++ b/drivers/crypto/sa2ul.c
@@ -33,10 +33,23 @@
#include "sa2ul.h"
-/* Byte offset for key in encryption security context */
-#define SC_ENC_KEY_OFFSET (1 + 27 + 4)
-/* Byte offset for Aux-1 in encryption security context */
-#define SC_ENC_AUX1_OFFSET (1 + 27 + 4 + 32)
+#define SC_ENC_MODESEL_OFFSET (0)
+#define SC_ENC_MODESEL_SIZE (1)
+
+#define SC_ENC_MCI_OFFSET (SC_ENC_MODESEL_SIZE)
+#define SC_ENC_MCI_SIZE (27)
+
+#define SC_ENC_KEY_OFFSET (SC_ENC_MCI_OFFSET + SC_ENC_MCI_SIZE + 4)
+#define SC_ENC_KEY_SIZE 32
+
+#define SC_ENC_AUX1_OFFSET (SC_ENC_KEY_OFFSET + SC_ENC_KEY_SIZE)
+#define SC_ENC_AUX1_SIZE 32
+
+#define SC_ENC_AUX2_OFFSET (SC_ENC_AUX1_OFFSET + SC_ENC_AUX1_SIZE)
+#define SC_ENC_AUX2_SIZE 16
+
+#define SC_ENC_AUX3_OFFSET (SC_ENC_AUX2_OFFSET + SC_ENC_AUX2_SIZE)
+#define SC_ENC_AUX3_SIZE 16
#define SA_CMDL_UPD_ENC 0x0001
#define SA_CMDL_UPD_AUTH 0x0002
@@ -45,7 +58,6 @@
#define SA_CMDL_PAYLOAD_LENGTH_MASK 0xFFFF
#define SA_CMDL_SOP_BYPASS_LEN_MASK 0xFF000000
-#define MODE_CONTROL_BYTES 27
#define SA_HASH_PROCESSING 0
#define SA_CRYPTO_PROCESSING 0
#define SA_UPLOAD_HASH_TO_TLR BIT(6)
@@ -229,7 +241,7 @@ struct sa_req {
* Mode Control Instructions for various Key lengths 128, 192, 256
* For CBC (Cipher Block Chaining) mode for encryption
*/
-static u8 mci_cbc_enc_array[3][MODE_CONTROL_BYTES] = {
+static u8 mci_cbc_enc_array[3][SC_ENC_MCI_SIZE] = {
{ 0x61, 0x00, 0x00, 0x18, 0x88, 0x0a, 0xaa, 0x4b, 0x7e, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
@@ -245,7 +257,7 @@ static u8 mci_cbc_enc_array[3][MODE_CONTROL_BYTES] = {
* Mode Control Instructions for various Key lengths 128, 192, 256
* For CBC (Cipher Block Chaining) mode for decryption
*/
-static u8 mci_cbc_dec_array[3][MODE_CONTROL_BYTES] = {
+static u8 mci_cbc_dec_array[3][SC_ENC_MCI_SIZE] = {
{ 0x71, 0x00, 0x00, 0x80, 0x8a, 0xca, 0x98, 0xf4, 0x40, 0xc0,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
@@ -261,7 +273,7 @@ static u8 mci_cbc_dec_array[3][MODE_CONTROL_BYTES] = {
* Mode Control Instructions for various Key lengths 128, 192, 256
* For CBC (Cipher Block Chaining) mode for encryption
*/
-static u8 mci_cbc_enc_no_iv_array[3][MODE_CONTROL_BYTES] = {
+static u8 mci_cbc_enc_no_iv_array[3][SC_ENC_MCI_SIZE] = {
{ 0x21, 0x00, 0x00, 0x18, 0x88, 0x0a, 0xaa, 0x4b, 0x7e, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
@@ -277,7 +289,7 @@ static u8 mci_cbc_enc_no_iv_array[3][MODE_CONTROL_BYTES] = {
* Mode Control Instructions for various Key lengths 128, 192, 256
* For CBC (Cipher Block Chaining) mode for decryption
*/
-static u8 mci_cbc_dec_no_iv_array[3][MODE_CONTROL_BYTES] = {
+static u8 mci_cbc_dec_no_iv_array[3][SC_ENC_MCI_SIZE] = {
{ 0x31, 0x00, 0x00, 0x80, 0x8a, 0xca, 0x98, 0xf4, 0x40, 0xc0,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
@@ -326,25 +338,25 @@ static u8 mci_ecb_dec_array[3][27] = {
* For CBC (Cipher Block Chaining) mode and ECB mode
* encryption and for decryption respectively
*/
-static u8 mci_cbc_3des_enc_array[MODE_CONTROL_BYTES] = {
+static u8 mci_cbc_3des_enc_array[SC_ENC_MCI_SIZE] = {
0x60, 0x00, 0x00, 0x18, 0x88, 0x52, 0xaa, 0x4b, 0x7e, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00,
};
-static u8 mci_cbc_3des_dec_array[MODE_CONTROL_BYTES] = {
+static u8 mci_cbc_3des_dec_array[SC_ENC_MCI_SIZE] = {
0x70, 0x00, 0x00, 0x85, 0x0a, 0xca, 0x98, 0xf4, 0x40, 0xc0, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00,
};
-static u8 mci_ecb_3des_enc_array[MODE_CONTROL_BYTES] = {
+static u8 mci_ecb_3des_enc_array[SC_ENC_MCI_SIZE] = {
0x20, 0x00, 0x00, 0x85, 0x0a, 0x04, 0xb7, 0x90, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00,
};
-static u8 mci_ecb_3des_dec_array[MODE_CONTROL_BYTES] = {
+static u8 mci_ecb_3des_dec_array[SC_ENC_MCI_SIZE] = {
0x30, 0x00, 0x00, 0x85, 0x0a, 0x04, 0xb7, 0x90, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00,
@@ -494,7 +506,7 @@ static int sa_set_sc_enc(struct algo_data *ad, const u8 *key, u16 key_sz,
const u8 *mci = NULL;
/* Set Encryption mode selector to crypto processing */
- sc_buf[0] = SA_CRYPTO_PROCESSING;
+ sc_buf[SC_ENC_MODESEL_OFFSET] = SA_CRYPTO_PROCESSING;
if (enc)
mci = ad->mci_enc;
@@ -502,7 +514,7 @@ static int sa_set_sc_enc(struct algo_data *ad, const u8 *key, u16 key_sz,
mci = ad->mci_dec;
/* Set the mode control instructions in security context */
if (mci)
- memcpy(&sc_buf[1], mci, MODE_CONTROL_BYTES);
+ memcpy(&sc_buf[SC_ENC_MCI_OFFSET], mci, SC_ENC_MCI_SIZE);
/* For AES-CBC decryption get the inverse key */
if (ad->inv_key && !enc) {
@@ -585,7 +597,7 @@ static int sa_format_cmdl_gen(struct sa_cmdl_cfg *cfg, u8 *cmdl,
SA_CMDL_HEADER_SIZE_BYTES + cfg->iv_size;
cmdl[enc_offset + SA_CMDL_OFFSET_OPTION_CTRL1] =
- (SA_CTX_ENC_AUX2_OFFSET | (cfg->iv_size >> 3));
+ (SC_ENC_AUX2_OFFSET | (cfg->iv_size >> 3));
total += SA_CMDL_HEADER_SIZE_BYTES + cfg->iv_size;
} else {
cmdl[enc_offset + SA_CMDL_OFFSET_LABEL_LEN] =
diff --git a/drivers/crypto/sa2ul.h b/drivers/crypto/sa2ul.h
index 0aa6a36c0f20..94101300736c 100644
--- a/drivers/crypto/sa2ul.h
+++ b/drivers/crypto/sa2ul.h
@@ -46,7 +46,6 @@ struct sa_tfm_ctx;
/* Number of 32 bit words in PS data */
#define SA_DMA_NUM_PS_WORDS 16
-#define MCI_SZ 27
/*
* Maximum number of simultaeneous security contexts
@@ -60,12 +59,6 @@ struct sa_tfm_ctx;
#define SA_CTX_SIZE_TO_DMA_SIZE(ctx_sz) \
((ctx_sz) ? ((ctx_sz) / 32 - 1) : 0)
-#define SA_CTX_ENC_KEY_OFFSET 32
-#define SA_CTX_ENC_AUX1_OFFSET 64
-#define SA_CTX_ENC_AUX2_OFFSET 96
-#define SA_CTX_ENC_AUX3_OFFSET 112
-#define SA_CTX_ENC_AUX4_OFFSET 128
-
/* Next Engine Select code in CP_ACE */
#define SA_ENG_ID_EM1 2 /* Enc/Dec engine with AES/DEC core */
#define SA_ENG_ID_EM2 3 /* Encryption/Decryption enginefor pass 2 */
@@ -142,12 +135,6 @@ struct sa_tfm_ctx;
*/
#define SA_CTX_SCCTL_OWNER_OFFSET 0
-#define SA_CTX_ENC_KEY_OFFSET 32
-#define SA_CTX_ENC_AUX1_OFFSET 64
-#define SA_CTX_ENC_AUX2_OFFSET 96
-#define SA_CTX_ENC_AUX3_OFFSET 112
-#define SA_CTX_ENC_AUX4_OFFSET 128
-
#define SA_SCCTL_FE_AUTH_ENC 0x65
#define SA_SCCTL_FE_ENC 0x8D
--
2.43.0