Re: [PATCH v12 06/12] cxl: Add CXL Device Reset helper
From: Lucero Palau, Alejandro
Date: Tue Sep 15 2026 - 10:05:23 EST
On 12/09/2026 02:26, Jonathan Cameron wrote:
On Thu, 10 Sep 2026 07:08:02 +0000
Srirangan Madhavan <smadhavan@xxxxxxxxxx> wrote:
Add an internal CXL Device Reset helper for Type 2 functions that
advertise CXL Reset and CXL Reset Memory Clear in the CXL Device DVSEC.
The helper disables CXL.cache, performs cache writeback when supported,
initiates reset with Memory Clear enabled, waits for completion, and
re-enables CXL.cache on exit.
Leave the helper unregistered until range validation and reset-scope
validation are in place.
Signed-off-by: Srirangan Madhavan <smadhavan@xxxxxxxxxx>
<snip>
+ if (dvsec < 0)Why do we need them both? Sure that's type 2, but a non
+ return dvsec;
+
+ if (!(cap & PCI_DVSEC_CXL_CACHE_CAPABLE) ||
+ !(cap & PCI_DVSEC_CXL_MEM_CAPABLE))
class code matching type3 would I think need the same infrastructure
you are building here. That would have cxl.mem but not cxl.cache
- I think some of the CXL SSD prototypes fit in this category.
Not sure if this reset path requires only Type2, but see my related comment below.
+ return -ENOTTY;
+
+ if (!(cap & PCI_DVSEC_CXL_RST_CAPABLE))
+ return -ENOTTY;
+ if (!(cap & PCI_DVSEC_CXL_RST_MEM_CLR_CAPABLE))
+ return -ENOTTY;
+
+ rc = pci_read_config_word(pdev, dvsec + PCI_DVSEC_CXL_CTRL, &ctrl);
+ if (rc)
+ return pcibios_err_to_errno(rc);
+
+ if (!(ctrl & PCI_DVSEC_CXL_CACHE_ENABLE) ||
+ !(ctrl & PCI_DVSEC_CXL_MEM_ENABLE))
+ return -ENOTTY;
Type2 cache support is coming and it could be CXL.cache forced to disable if IOMMU enabled and the device not supporting ATS nor belonging to IOMMU identity mapping (Benjamin Cheatham will send this support soon). In that case, I can not see a reason for not allowing a reset assuming CXL.mem would be still usable independently of CXL.cache functionality.